Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-05-24
2001-07-24
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S302000, C257S305000, C257S303000, C257S331000, C365S174000, C365S177000, C365S182000
Reexamination Certificate
active
06265742
ABSTRACT:
This invention relates to memory cells, and more particularly, to memory cells of the kind that are arranged in large arrays in a silicon chip to form a dynamic random access memory (DRAM).
BACKGROUND OF THE INVENTION
DRAMs have become one of the most important of integrated circuit devices. The memory cell of a state of the art DRAM comprises a switch, generally an MOS transistor, and a storage capacitor, generally a trench capacitator. Memory cells of this kind in the millions are formed in a single chip of silicon and arranged in rows and columns. These are addressed by bit lines and word lines of auxiliary circuits that read in and read out binary digits (bits) stored in the capacitors.
The trend is to even higher and higher density of memory cells in a single chip. This requires that the cells be made smaller and smaller to permit higher and higher packing density. Typically, the memory cell of a DRAM uses for storage a capacitor that is formed by a polysilicon-filled trench that is isolated from the monocrystalline bulk of the chip by a dielectric layer that serves as the capacitor dielectric. The switch of the cell is formed by an MOS transistor in the monocrystalline bulk that has one of its current terminals, to be termed the drain, conductively connected to the polysilicon fill of the trench and the other, to be termed the source, connected to the bit line of the DRAM. Moreover, a recent innovation is to form the transistor as a vertical transistor located over the trench to save surface area of the silicon chip and so permit a higher packing density of cells in the chip.
One of the major problems posed by this kind of switching transistor is the need to form its most critical region, the base in which is formed the conductive channel when the transistor is closed, in essentially monocrystalline silicon, if the transistor is to have desired switching characteristics.
The present invention seeks to provide an improved solution to this problem.
SUMMARY OF THE INVENTION
In one aspect the present invention is directed to a method of forming a memory cell adaptable for integration into large arrays to form a DRAM. As is customary, most of the processing is carried out in a large wafer that is subsequently diced up into individual silicon chips, each of which will contain a very large number of memory cells arranged in rows and columns along with the auxiliary circuits that provide the bit and word lines that provide access to the individual cells.
A feature of the novel method is that there is formed in the top portion of a deep trench that is used for the storage capacitor a layer of silicon that has been grown epitaxially from adjacent monocrystalline silicon that is part of the original monocrystalline bulk of a silicon wafer.
In one form of the invention, a pair of switching transistors, each having its epitaxial silicon body or base in a different trench, share a common source that is formed in the original bulk between the two trenches.
From the process aspect the present invention is directed to a specific method for forming a memory cell for use in a dynamic random access memory including a transistor in series with a capacitor. The basic steps of this specific method are: preparing a semiconductive wafer whose active bulk where the cell is being formed is monocrystalline; forming a vertical trench at the top surface of the active bulk of the wafer; forming a first dielectric layer over the walls of the trench suitable for use as the dielectric of the capacitor; filling the trench with polysilicon; forming a first recess in the polysilicon fill; forming a collar dielectric layer thicker than the first dielectric layer over the walls of the first recess; refilling the trench with polysilicon; forming a second recess in the trench of a second depth less than the first depth; removing all dielectric from the walls of said second recess for exposing bulk monocrystalline silicon; refilling the second recess by growing silicon epitaxially from the exposed bulk monocrystalline silicon; etching for exposing a portion of the surface of the epitaxially grown silicon; forming over the exposed surface of the epitaxially grown silicon a dielectric layer suitable for use as the gate dielectric of the transistor; forming over the gate dielectric a conductive layer for serving as the gate conductor of the transistor; and forming a conductive layer in contact with the top of the epitaxial fill for serving as the source of the transistor with a buried portion of the polysilicon fill of the trench serving as the drain of the transistor.
In an embodiment, the method of the invention is more particularly as follows. First there is prepared a silicon wafer that is essentially monocrystalline and has at least an active surface portion that is of p-type conductivity. After the customary PAD layer has been formed over the top surface, the layer is patterned to define the various active areas that are to house pairs of individual memory cells. Then a relatively deep vertical trench typically of essentially circular cross section, is formed separately where each capacitor of each pair of memory cells is to be housed. The walls of the trench are now covered with a relatively thin, insulating layer that will serve as the dielectric layer of the capacitor. Each trench is now filled with n-type doped polysilicon. Then a relatively deep first recess is formed in each trench and the relatively thin insulating layer is removed from the recessed portion of each trench and replaced with a thicker insulating collar. The first recess in each trench is now refilled with n-type doped polysilicon. Then a second, relatively shallow, recess is formed in each trench, after which the collar portion exposed in the second recess is removed to bare along the side wall of this second recess monocrystalline silicon that is part of the original bulk. This second recess is now refilled with a silicon region that has been grown epitaxially from the bared monocrystalline silicon bulk. Next, isolation trenches are formed over the wafer to isolate from one another the active areas where pairs of memory cells are to be formed. These isolation trenches essentially bisect the silicon regions that were grown epitaxially. Then these isolation trenches are filled with silicon oxide and the silicon oxide is patterned to expose the surface of the bisected portions of the individual epitaxial regions and provide recesses where gate conductors can be provided for the transistors. However, first a silicon oxide layer is formed over the exposed epitaxial silicon regions to provide the transistor gate dielectric, after which the gate conductors are deposited in the recesses. Finally, there is bared a surface portion of the original bulk intermediate between the top surfaces of the two associated epitaxial silicon regions enclosed within the shallow isolation trenches, and a source region is formed there that serves a a common source for the pair of adjacent transistors within each active area. Finally the separate gate conductors of the pair of adjacent transistors are connected to separate word lines and their common source is connected to a common bit line.
With respect to the product aspect of the invention, there results a memory cell in which the switching transistor has a source, which it shares with an adjacent transistor of another memory cell, that is largely in the original monocrystalline bulk, a drain that is largely buried deep in the vertical trench, and an epitaxial base or body region that provides an essentially vertical channel in the vertical trench, and the storage capacitor has its storage node deep in the vertical trench and its other plate in the original bulk. As a result, little of the top surface of the wafer is used in providing the memory cell and the channel of its transistor is formed in epitaxial silicon fill of the vertical trench that also provides its storage capacitor.
Moreover, by locating a pair of square vertical trenches on opposite sides of a square central bulk portion, each trench being of
Beintner Jochen
Gruening Ulrike
Joachim Hans-Oliver
Braden Stanton C.
Lee Eddie
Siemens Aktiengesellschaft
Wilson Allan R.
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