Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-04-08
2001-08-14
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S173000, C257S174000, C257S328000, C257S487000, C257S356000, C257S357000, C257S358000, C257S359000, C257S360000, C257S546000
Reexamination Certificate
active
06274908
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a MOS transistor formed on a SOI substrate, and more particularly to an input-output protecting function thereof.
2. Description of the Background Art
In the case where a MOS device is formed on a bulk silicon substrate, a surge can be discharged into the substrate through a PN junction. In a SOI (Silicon-on-insulator) device in which the MOS device is formed on a SOI layer provided on a buried insulation layer, a path for transferring the surge does not structurally exist on the substrate because the buried insulation layer is formed. In particular, a longitudinal discharge path does not exist in a thin film SOI structure in which source and drain regions of a MOS transistor reach a buried oxide film. Consequently, it is structurally necessary to perform a transverse discharge. For this reason, the discharge is transversely performed into a power line and a grounding line through the MOS transistor and a diode.
FIG. 31
is a circuit diagram showing a structure of an input-output protecting circuit having a SOI structure according to the prior art. As shown in
FIG. 31
, one of ends of a resistor
36
(hereinafter referred to as a “protecting resistor”) for limiting a rush current is first connected to a signal terminal
30
to delay propagation of a surge voltage to an inside through the signal terminal
30
, thereby preventing an excessive current from flowing. Then, a PMOS transistor Q
31
and an NMOS transistor Q
32
are provided in series as discharge elements for transferring electric charges between a power supply (node)
32
and a ground level (node)
33
. The PMOS transistor Q
31
and the NMOS transistor Q
32
have gates connected to the power supply
32
and the ground level
33
, and drains connected to the other end of the protecting resistor
36
in common, respectively. Accordingly, the PMOS transistor Q
31
and the NMOS transistor Q
32
are usually brought into an OFF state.
In the case where the surge voltage is applied to the signal terminal
30
, the electric charges are quickly discharged into the power supply
32
or the ground level
33
by avalanche breakdown of each of the MOS transistors Q
31
and Q
32
to protect an internal element
31
. Furthermore, the other end of the protecting resistor
36
is connected to one of ends of an internal resistor
37
, and the internal element
31
is connected to the other end of the internal resistor
37
. Consequently, the surge voltage is propagated to the internal element
31
with difficulty.
FIG. 32
shows an input-output protecting circuit formed by using diodes
38
and
39
as discharge elements in the same manner. As shown in
FIG. 32
, one of ends of a protecting resistor
36
is first connected to a signal terminal
30
to delay propagation of a surge voltage to an inside through the signal terminal
30
, thereby preventing an excessive current from flowing. Then, the diodes
38
and
39
are provided in series as discharge elements for transferring electric charges between a power supply
32
and a ground level
33
. A cathode of the diode
38
is connected to the power supply
32
, and an anode of the diode
39
is connected to the ground level
33
. Accordingly, the diodes
38
and
39
are connected in reverse directions between the power supply
32
and the ground level
33
.
If the surge voltage is applied to the signal terminal
30
, the electric charges are quickly discharged into the power supply
32
or the ground level
33
by backward avalanche breakdown of the diodes
38
and
39
or a forward current, thereby protecting an internal element
31
. Furthermore, an internal resistor
37
is inserted between the protecting resistor
36
and the internal element
31
to propagate the surge voltage to the internal element
31
with difficulty.
FIG. 33
shows an inverter circuit acting as one of typical internal circuits. As shown in
FIG. 33
, a PMOS transistor Q
33
and an NMOS transistor Q
34
are connected in series between a power supply
32
and a ground level
33
. The PMOS transistor Q
33
and the NMOS transistor Q
34
have gates connected to an input signal terminal
82
in common, and drains connected to an output signal terminal
83
in common.
In the case where the input-output protecting circuits having the structures shown in
FIGS. 31 and 32
are connected to the input signal terminal
82
(an input section of the internal circuit) for the internal circuit shown in
FIG. 33
, they function as input protecting circuits. In the case where the same input-output protecting circuits are connected to the output signal terminal
83
(an output section of the internal circuit), they function as output protecting circuits. The function and operation of the protecting circuit are the same in the input and output sections. Therefore, the protecting circuit will be hereinafter referred to as an “input-output protecting circuit”. If the protecting circuit is used as the output protecting circuit, no resistor is often added thereto.
FIG. 34
is a plan view showing a planar structure of the MOS input-output protecting circuit shown in
FIG. 31
, and
FIG. 35
is a sectional view taken along the line A—A shown in FIG.
34
. As shown in
FIGS. 34 and 35
, a thin silicon film
3
acting as a SOI layer is provided on a silicon substrate
1
with a buried oxide film
2
acting as an insulation layer interposed therebetween. The thin silicon film
3
is divided into two islands
18
A and
18
B by an interlayer dielectric film
11
. Channel formation regions
6
and
6
d
into which an impurity having a concentration of about 10
17
/cm
3
(p-type in NMOS and n-type in PMOS) is implanted are provided, drain and source regions
7
and
8
into which an impurity having a concentration of about 10
20
/cm
3
(n-type in NMOS and p-type in PMOS) is implanted are provided with the channel formation region
6
interposed therebetween, and drain and source regions
7
d
and
8
d
into which an impurity having a concentration of about 10
20
/cm
3
is implanted are provided with the channel formation region
6
d
interposed therebetween. Furthermore, gate electrodes
5
and
5
d
are formed on the channel formation regions
6
and
6
d
and a part of each of the drain regions
7
and
7
d
and the source regions
8
and
8
d
in the thin silicon film
3
with gate oxide films
4
and
4
d
interposed therebetween, respectively. Accordingly, the NMOS transistor Q
32
is formed by the gate oxide film
4
, the gate electrode
5
, the channel formation region
6
, the drain region
7
and the source region
8
in the island
18
A, and the PMOS transistor Q
31
is formed by the gate oxide film
4
d,
the gate electrode
5
d,
the channel formation region
6
d,
the drain region
7
d
and the source region
8
d
in the island
18
B.
Furthermore, the interlayer dielectric film
11
divides the thin silicon film
3
into the islands
18
A and
18
B and is formed over the whole surface of the thin silicon film
3
. Contact holes
12
A to
12
D are provided on the interlayer dielectric film
11
in a part of each of the drain regions
7
and
7
d
and the source regions
8
and
8
d.
An aluminum wiring
14
is electrically connected to the drain regions
7
and
7
d
through the contact holes
12
A and
12
B, an aluminum wiring
13
is electrically connected to the source region
8
through the contact hole
12
C, and an aluminum wiring
15
is electrically connected to the source region
8
d
through the contact hole
12
D. The aluminum wiring
13
is connected to a ground level
33
, the aluminum wiring
14
is connected to an input section
30
d,
and the aluminum wiring
15
is connected to a power supply
32
. The input section
30
d
means a portion to be connected to the other end of the protecting resistor
36
as shown in FIG.
32
. In
FIG. 34
, the interlayer dielectric film
11
is omitted.
As shown in
FIG. 34
, the protecting resistor
36
formed of a gate electrode material and a thin silicon fil
Ippooshi Takashi
Yamaguchi Yasuo
Abraham Fetsum
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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