Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-23
2001-03-13
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S391000, C257S392000, C257S393000, C438S275000, C438S276000, C438S291000
Reexamination Certificate
active
06201282
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to dual bit cells generally and to dual bit mask programmable array cells and their methods of manufacture in particular.
BACKGROUND OF THE INVENTION
Dual bit cells are known in the art although they are not common. Some dual bit cells have multiple threshold levels, where every two threshold levels together store a different bit. Others store one bit on either side of the cell. A dual bit cell of the latter kind, known as nitride read only memory (NROM) cell, is described in Applicant's copending U.S. patent application Ser. No. 08/905,286, entitled “Two Bit Non-Volatile Electrically Erasable And Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping” which was filed Aug. 1, 1997 and was assigned to the common assignee of the present invention. The disclosure of the above-identified application is incorporated herein by reference.
FIG. 1
, to which reference is now made, schematically illustrates the dual bit NROM cell. The cell has a single channel
100
between two bit lines
102
and
104
but two separated and separately chargeable areas
106
and
108
.
Each area defines one bit. For the dual bit cell of
FIG. 1
, the separately chargeable areas
106
and
108
are found within a nitride layer
110
formed in an oxide-nitride-oxide sandwich (layers
109
,
110
and
111
) underneath a polysilicon layer
112
.
To read the left bit, stored in area
106
, right bit line
104
is the drain and left bit line
102
is the source. This is known as the “read through” direction. The cell is designed to ensure that, in this situation, only the charge in area
106
will affect the current in channel
100
. To read the right bit, stored in area
108
, the cell is read in the opposite direction. Thus, left bit line
102
is the drain and right bit line
104
is the source.
Like floating gate cells, the cell of
FIG. 1
is erasable and programmable. Thus, the charge stored in areas
106
and
108
can change over time in response to a user's request.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a dual bit, mask programmable array, such as the read only memory (ROM) type whose data is fixedly stored therein.
In accordance with a preferred embodiment of the present invention, each cell is a dual bit cell. The bits are separately stored in two different portions of the channel, where a programmed bit has a threshold pocket implant in the relevant portion of the channel. For example, the portions might be the left and right bit line junctions of the channel, where a programmed bit has a threshold pocket implant self-aligned to its bit line junction and an unprogrammed bit has no such implant.
In accordance with a preferred embodiment of the present invention, the array is manufactured by laying down a bit line mask and then implanting the bit lines in the spaces between the masks. The bit line mask can be formed from ultraviolet hardened photoresist or from a thick oxide layer.
The left and right bits are then separately created. For each type of bit, the bit line junctions which are to remain unprogrammed are first covered, with a junction mask. To program the channels whose left or right bit lines are uncovered, the array is exposed to a threshold pocket implant at a 15-45° angle to the right or to the left, respectively, which accesses the left or right bit line junction of the channels through the uncovered bit lines. This provides a self-aligned pocket implant (i.e. a programmed bit) in the bit line junctions of channels whose left or right bit lines, respectively, are exposed. The other exposed junctions are not implanted due to shadowing from the bit line mask.
The junction mask is removed and the other set of this produced in a similar manner, except that the angle of the threshold pocket implant is in the opposite direction. The bit line mask is removed and a gate oxide layer is grown or deposited over the array. If the gate oxide layer is grown, then the oxide over the bit line is thicker than that over the gate due to the presence of implant in the bit line. The gates of all of the transistors of the chip and the word lines connecting them are then deposited. The chip is then finished according to the standard CMOS process.
For processes which grow a very thin gate oxide layer (less than 150), an extra gate oxide cycle can be utilized which grows a thicker gate oxide the ROM portion of the chip. The thicker gate oxide layer reduces the amount of Boron needed to raise the threshold levels of the transistors so as to turn them off.
In an alternative embodiment of the present invention, the bit line implant occurs after the threshold voltage (i.e. programming) implant operations.
In a further alternative embodiment of the present invention, the pocket implant can be produced with two different materials, such as Boron and Arsenic or Phosphorous.
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Darby & Darby
Ortiz Edgardo
Saadat Mahshid
Saifun Semiconductors Ltd.
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