Semiconductor memory device and method of fabricating the same

Details Semiconductor memory device and method of fabricating the same Semiconductor memory device and method of fabricating the same

1999-10-12

2001-01-16

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S298000

Reexamination Certificate

active

06175132

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an improvement in a semiconductor memory such as a dynamic random access memory having a stacked capacity, which has a sloped or stepped region at a boundary between a first region in which a memory cell is formed and a second region in which a peripheral circuit is formed.
2. Description of the Related Art
In these days, a dynamic random access memory (DRAM) device having a stacked capacity has been designed to include an accumulation electrode having an increased thickness, in order to ensure an accumulation capacity as much as possible. However, if an accumulation electrode is designed to have an increased thickness, it is unavoidable that a sloped or stepped region is formed at a boundary between a first region in which a memory cell is formed and a second region in which a peripheral circuit is formed.
In such a semiconductor memory device having a sloped or stepped region, it would be often impossible to ensure sufficient focus margin, and hence, it would be also impossible to pattern a wiring layer in a photolithography step to be carried out subsequent to formation of an accumulation electrode. In addition, such a semiconductor memory device is accompanied with a problem that some portions are not etched in an etching step. As a result, a resultant semiconductor memory device would have problems of breakage in a wiring and short-circuit. Furthermore, since it is quite difficult to accurately pattern a layer, design-rule for making a small-sized device cannot be applied to such a semiconductor memory device.
An example of a semiconductor memory device having a sloped or stepped region is illustrated in
FIGS. 1 and 2
.
The illustrated semiconductor memory device is comprised of a p-type semiconductor substrate
1
, a field oxide film
2
formed at a surface of the p-type semiconductor substrate
1
, gate electrodes
4
formed on the p-type semiconductor substrate
1
, n-type diffusion layers
3
formed around the gate electrodes at a surface of the p-type semiconductor substrate
1
, a first interlayer insulating film
5
covering the substrate
1
therewith, first contacts
6
formed throughout the first interlayer insulating film
5
and reaching the n-type diffusion layers
3
, accumulation electrodes
7
formed on the first interlayer insulating film
5
and making electrical connection with the n-type diffusion layers
3
through the first contacts
6
, a plate electrode
8
covering the accumulation electrodes
7
therewith, a second interlayer insulating film
9
formed on the plate electrode
8
and the first interlayer insulating film
5
, a second contact
10
formed throughout the first and second interlayer insulating films
5
and
9
, and reaching the n-type diffusion layer
3
, and wiring layers
11
,
12
,
13
and
14
formed on the second interlayer insulating film
9
.
As illustrated in
FIG. 1
, the semiconductor memory device has a first region in which a memory cell is formed and a second region in which a peripheral circuit is formed.
The illustrated semiconductor memory device is fabricated as follows.
First, a field oxide film
2
is formed on a p-type semiconductor substrate
1
by thermal oxidation by a thickness of 0.4 &mgr;m. An area surrounded by the field oxide film
2
defines an area in which a device is to be fabricated.
Then, an n-type polysilicon film is formed on the p-type semiconductor substrate
1
by a thickness of 0.2 &mgr;m. The thus deposited n-type polysilicon is patterned by photolithography to thereby form gate electrodes
4
.
Then, the p-type semiconductor substrate
1
is ion-implanted with doses of about 5×10
13
phosphorus (P) cm
−2
in self-aligning fashion about the gate electrodes
4
and the field oxide film
2
, to thereby form n-type diffusion layers
3
in the p-type semiconductor substrate
1
.
Then, a first interlayer insulating film
5
is formed over the p-type semiconductor substrate
1
, and subsequently, first contacts
6
are formed throughout the first interlayer insulating film
5
so that they reach the n-type diffusion layers
3
.
Then, a doped polysilicon film is formed all over the first interlayer insulating film
5
by a thickness of 0.8 &mgr;m. The thus deposited polysilicon film is patterned to thereby form accumulation electrodes
7
on the first contacts
6
.
Then, a capacitive insulating film (not illustrated) is formed over a resultant. Then, a polysilicon film is formed by a thickness of 0.2 &mgr;m, and is pattered into plate electrodes
8
.
Then, a second interlayer insulating film
9
is deposited all over a resultant by a thickness of 0.5 &mgr;m. The second interlayer insulating film
9
is composed of BPSG (boron phospho silicate glass), for instance.
Then, wiring layers
11
to
14
are formed on the second interlayer insulating film
9
. The wiring layers
11
to
14
are composed of aluminum, for instance.
Thus, there is completed the semiconductor memory device illustrated in
FIGS. 1 and 2
.
As illustrated in
FIG. 1
, there is formed a relatively steep stepped region
15
around a boundary between the first and second regions, specifically, in a region A sandwiched between the wiring layers
11
and
13
. Thus, it is quite difficult to accurately pattern an aluminum film for forming the wiring layers
11
to
14
. In particular, since a photoresist layer for making the wiring layer
12
located in the region A would have a great thickness in a photolithography step, it would be quite difficult to accurately pattern the aluminum film into the wiring layer
12
.
In addition, there remains residue
19
of a wiring layer in the region A, after an etching step has been carried out.
There have been suggested many attempts to ease steep of the stepped region. For instance, Japanese Unexamined Patent Publications Nos. 4-82263, 4-87366, 6-5803, and 6-216332 have suggested a semiconductor memory device making attempts to ease steep of a stepped region formed between the first and second regions by forming a dummy pattern at a boundary between the first and second regions.
FIGS. 3 and 4
illustrate an example of a semiconductor memory device suggested in the above-mentioned Publications.
The illustrated semiconductor memory device is comprised of a p-type semiconductor substrate
1
, a field oxide film
2
formed at a surface of the p-type semiconductor substrate
1
, gate electrodes
4
formed on the p-type semiconductor substrate
1
, n-type diffusion layers
3
formed around the gate electrodes at a surface of the p-type semiconductor substrate
1
, a dummy gate pattern
16
formed above a field oxide film
2
a
, a first interlayer insulating film
5
covering the substrate
1
therewith, first contacts
6
formed throughout the first interlayer insulating film
5
and reaching the n-type diffusion layers
3
, accumulation electrodes
7
formed on the first interlayer insulating film
5
and making electrical connection with the n-type diffusion layers
3
through the first contacts
6
, a plate electrode
8
covering the accumulation electrodes
7
therewith, a second interlayer insulating film
9
formed on the plate electrode
8
and the first interlayer insulating film
5
, a second contact
10
formed throughout the first and second interlayer insulating films
5
and
9
, and reaching the n-type diffusion layer
3
, and wiring layers
11
,
12
,
13
and
14
formed on the second interlayer insulating film
9
.
In the semiconductor memory device illustrated in
FIGS. 3 and 4
, since the dummy gate pattern
16
is formed above the relatively long field oxide film
2
a
, steep
15
a
of the stepped region formed between the first and second regions is made smaller than the steep
15
of the stepped region in the semiconductor memory device illustrated in
FIGS. 1 and 2
.
However, a region B sandwiched between the wiring layers
11
and
13
in the semiconductor memory device illustrated in
FIG. 3
is longer than the region A in the semiconductor memory device illustrated in FIG.
1
. This mean

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