Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
1999-08-09
2001-03-20
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S040000
Reexamination Certificate
active
06204685
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of implementing a fast path with a dual-function macrocell in a product-term based programmable device generally and, more particularly, to a complex programmable logic device (CPLD) architecture.
BACKGROUND OF THE INVENTION
In one previous architecture, fast paths in a Generic Logic Block (GLB) in a product term based CPLD were identified by the term “PT Bypass” (see the 1000, 2000, and 3000 families of CPLDs available commercially from Lattice Semiconductor Corporation, Hillsboro, Oregon). The same scheme was used in all three families, and is shown in their 1994 data book (pp. 2-12, 2-13, 2-14, 2-21, 2-26, and 2-32).
The figure on page 2-12 of the data book shows the number and allocation of product terms in the GLB. The figures on page 2-13 show how the fast path is implemented and how the XOR gate can be used. The figure on page 2-14 provides an example of another configuration of the GLB where the second of the four macrocells uses a fast path. A timing model is shown on page 2-21 of the data book indicating that the “4 PT Bypass” is the fastest path through a portion of the GLB. The figures on page 2-26 and page 2-32 indicate that the same scheme has been propagated to the 2000 and 3000 family architectures.
The disadvantage of the Lattice method is that when the “4 PT Bypass” is used, the capability that was previously available for that macrocell is completely lost. The previous capability includes an XOR gate or an OR gate with up to 20 PTs.
SUMMARY OF THE INVENTION
The present invention concerns a logic block in a product-term based programmable device comprising a first logic gate, a second logic gate, a macrocell and a multiplexer. The first logic gate may be configured to generate a first output in response to a logical combination of a first number of product terms. The second logic gate may be configured to generate a second output in response to a logical combination of a second number of product terms. The macrocell may be configured to generate a third output in response to the second output. The multiplexer may be configured to select an output of the device in response to (i) the first output or (ii) the third output. The first number of product terms may be a subset of the second number of product terms.
The objects, features and advantages of the present invention include implementing a programmable device that may (i) provide a faster path through a programmable logic block architecture, (ii) implement dual functionality, such as a fast combinatorial path and a buried macrocell, and/or (iii) implement a superset capability to previous commercial architectures.
REFERENCES:
patent: 5220214 (1993-06-01), Pedersen
patent: 5350954 (1994-09-01), Patel
patent: 5414376 (1995-05-01), Hawes
patent: 5523706 (1996-06-01), Kiani et al.
1000 Family Architectural Description—Generic Logic Block, 1994 Data Book, pp. 2-12 to 2-14.
1000 Family Architectural Description—Timing Model, 1994 Data Book, pp. 2-21.
2000 Family Architectural Description , 1994 Data Book, pp. 2-26.
3000 Family Architectural Description—Generic Logic Block, 1994 Data Book, pp. 2-32.
Cypress Semiconductor Corp.
Le Don Phu
Maiorana P.C. Christopher P.
Tokar Michael
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