Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
1998-12-18
2001-03-20
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S071000, C382S232000, C382S244000
Reexamination Certificate
active
06205499
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to video signal encoding systems. More particularly, the present invention is concerned with a digital encoding system for encoding video signals which uses bi-orthogonal wavelet coding to compress digitized video data.
2. Description of the Prior Art
There is currently a need for the reliable transmission and reception of real time television video and/or television sub video over a narrow bandwidth. For example, in the transmission of telemetry video data from a missile the telemetry channel may have a bandwidth of two megahertz or even substantially less than two megahertz.
Prior art methods and apparatus for compressing real time video data include Adaptive Differential Pulse Code modulation (ADPCM), Joint Photography Experts Group (JPEG) and Motion Picture Experts Group (MPEG). These methods of encoding real time video data are generally not capable of sufficient bandwidth reduction or are susceptible to excessive data loss in a noisy environment.
For example, Adaptive Differential Pulse Code modulation, which is used by the International Range Instrumentation Group to transmit telemetry data, is noise immune, however, it is not capable of real time video data compression to allow accurate and reliable transmission of the data over a channel narrower than five megahertz. Even moderately complex video images overload an ADPCM encoder causing it to lose fields and even multiple frames of video data.
Both Joint Photography Experts Group and Motion Picture Experts Group methods and encoders are capable of compressing real time video data sufficiently to allow the data to be transmitted over a two megahertz channel, however, these methods and encoders are susceptible to noise. A single noise hit, for example, can cause the lose of an entire video field or even multiple fields. In addition, JPEG and MPEG encoding can distort an image with the random appearance of square blocks caused in a noisy environment by a reflection of eight by eight pixel discrete cosine transform used encode the video data.
Accordingly, there is a need for an encoder to accurately and reliably encode complex video data which allow for its transmission over a bandwidth of two megahertz without distortion of the data caused by noise.
SUMMARY OF THE INVENTION
The present invention overcomes some of the disadvantages of the prior art including those mentioned above in that it comprises a highly reliable and effective encoder for compressing video data to allow for its transmission over a narrow bandwidth of two megahertz or less.
The video encoder of the present invention comprises a multiformat video codec which is a video encoder optimized for real-time compression of interlaced digital data and a dynamic random access memory coupled to the multiformat video codec. The dynamic random access memory functions as a temporary storage device storing compressed data while the codec is compressing video data.
Multiformat video codec also has connected thereto a digital signal processor which adjust the data compression ratio for codec while the codec is compressing video data. Digital signal processor monitors the quantity or amount of compressed 32 bit words provided by codec during each field of video data to adjust the data compression ratio. There is also connected to the digital signal processor an EPROM which contains the software to run digital signal processor.
A microcontroller which is connected to the multiformat video codec is used to initialize the codec upon power up providing the contents of the bin width registers, reset commands and the initial compression ratio to the multiformat video codec.
Coupled to the multiformat video codec is a programmable gate array which operates as an interface between the codec and an external host processor. The programmable gate array converts parallel data from the codec to serial data for transmission to the external host processor and also provides a constant serial data rate to the external host processor.
The programmable gate array includes a read write controller which provides a read signal to the codec to allow compressed video data to be read from the codec and then supplied to an eight bit parallel to serial shift register within the gate array. The write control signals which allow data to be written into and shifted through the parallel to serial shift register are also generated by the programmable gate array. The programmable gate array includes a FIFO flush data controller which is used to flush data from a FIFO within the codec whenever the codec supplies a service request signal to the programmable gate array. The service request signal is provided to the array whenever an overflow condition is about to occur within the FIFO of the codec. Compressed video data is then flushed out of the FIFO within the codec.
The codec also provides a FIFO stop signal to the gate array which indicates that the FIFO within the codec is empty. The programmable gate array then sets a FIFO_MASK flag to a logic one state t
0
prevent a read operation of the FIFO within the codec. A dummy Mallet block is generated by the gate array and transmitted to the external host processor.
REFERENCES:
patent: 5159336 (1992-10-01), Rabin et al.
patent: 5838377 (1998-11-01), Greene
patent: 6115341 (2000-09-01), Hirai
patent: 6122310 (2000-09-01), Ziemer et al.
patent: 6125201 (2000-09-01), Zador
patent: 6139197 (2000-10-01), Banks
patent: 6144773 (2000-11-01), Kolarov et al.
Houlberg Christian L.
McPartland Philip J.
Du Thuan
Kalmbaugh David
Lee Thomas
The United States of America as represented by the Secretary of
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