Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-11-17
2001-09-11
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C711S100000
Reexamination Certificate
active
06289470
ABSTRACT:
BACKGROUND OF THE INVENTION
1 . Field of the Invention
The present invention relates to a memory circuit for storing data handled inside a microcomputer, for example, a data monitor circuit for specifying failures of a readable and writable random access memory (hereinafter referred to as a RAM), or an electrically erasable read only memory (hereinafter referred to as EEPROM) etc.
2. Description of the Related Art
Recently, the degree of integration and efficiency of microcomputers has been improving rapidly. Such a microcomputer is constructed by integrating various component elements on to a single integrated circuit chip (hereinafter simply called a chip). Particularly, the typical microcomputer structure has a central processing unit for carrying out operational control of each component element within the microcomputer, a first memory circuit, such as RAM or EEPPROM for storing data to be handled in the microcomputer, a second memory circuit, such as read only memory (hereinafter referred to as ROM) for storing program data for various processes of the microcomputer, and a bus for sending address information and data of the memory circuits.
In this type of microcomputer, failures occur in the internal memory for storing data. Analysis of these failures involves executing writing and reading of data to and from the memory, and specifying failed locations according to the state of the read data.
However, by only executing writing and reading of data to and from the memory for simply storing data, as described above, it takes time to find the failed locations, or failed locations can not be found. For example, when failures occur in a memory for storing data after execution of specified processing set within a program, the execution of that specified processing can also be the main cause of major failures. In this type of situation, it is better if a program for checking failed locations can be inserted within the program, and failed locations specified during execution of the program for reproducing the failure phenomenon.
However, a mask ROM is used in a ROM storing the program, and a checking program within the memory internal to a microcomputer, such as a one time program type microcomputer (hereinafter referred to as OTP) can not be updated. This means that a check program can not be inserted into the program, and there is a problem that failure analysis can not be performed.
An object of the present invention is to solve the above problems by reliably carrying out failure analysis during execution of a program.
A further object of the present invention is to reliably carry out failure analysis during execution of a program with a simple construction.
Another object of the present invention is to reliably carry out failure analysis during execution of a program at high speed.
A still further object of the present invention is to reliably carry out failure analysis during execution of a program, even under complex conditions.
SUMMARY OF THE INVENTION
At least reading of data from a first memory circuit is carried out via a bus according to a fixed program, and a data monitor circuit for monitoring data transferred on this bus comprises a first address storage circuit for storing information of an address of the memory circuit to be monitored, a first comparison circuit for receiving address information designated by a fixed program via a bus and detecting coincidence with address information stored in the first address storage circuit, a first data storage circuit for storing data being transferred on the bus, a first gate circuit for transferring data being transferred to the bus to the first data storage circuit in response to a first permission signal, and a control circuit for outputting the first permission signal according to a detection result of the first comparison circuit.
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Iqbal Nadeem
Wilmington Trust Company
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