Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1998-12-18
2001-04-24
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S774000, C257S775000
Reexamination Certificate
active
06222268
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a method for manufacturing the same. More particularly, the invention relates to a semiconductor device structured suitably to have contacts self-aligned therein, as well as to a method for manufacturing that semiconductor device.
2. Description of the Background Art
Along with the ever-growing scale in recent years of circuit integration in semiconductor devices has come wiring patterns getting more minuscule than ever before. The trend is making it progressively difficult to ensure the precision of wiring patterns by merely raising the accuracy of masking for photoresist. Illustratively, with memory cells getting finer than ever, boosting the masking accuracy is increasingly liable to fail in having contacts fabricated on such memory devices as DRAMs without short-circuiting their wiring. One known method for producing contacts without developing short-circuits with wiring has recourse to what is known as self-alignment. The conventional self-alignment method will now be described with reference to
FIGS. 29 through 31
.
Manufacturing contacts conventionally by self-alignment involves first forming an insulating film
12
on a silicon substrate
10
as shown in FIG.
29
. On top of the insulating film
12
are formed silicon wiring
14
and nitride film top walls
16
.
As shown in
FIG. 30
, nitride film side walls
18
to protect the silicon wiring
14
are formed laterally onto the silicon wiring
14
and the nitride film top walls
16
. At this stage, the silicon wiring
14
is covered with the nitride films
16
and
18
.
An interlayer oxide film
20
(see
FIG. 31
) is deposited all over the silicon substrate
10
, being masked at suitable portions by photoresist and being subjected to an oxide film etching process. This produces contact holes
22
. The oxide film etching process is done in a manner that causes removing the oxide film
20
at a sufficient selective ratio to nitride film. That is, the nitride film top walls
16
and nitride film side walls
18
remain virtually undamaged by the etching.
If the portions not masked by photoresist are sufficiently wide relative to the pitch of the silicon wiring
14
, not only the interlayer oxide film
20
but also the nitride films
16
and
18
would be involved in an subjected area of the etching in the midst of the process. In this case, the nitride films
16
and
18
act as stoppers against the oxide film etching whose progress is impeded thereby. This manufactures contact holes
22
opened to the surface of the silicon substrate
10
without exposing the silicon wiring
14
, as shown in FIG.
31
.
A silicon film is then deposited in the contact holes
22
and formed to a desired shape. As a result, contacts
24
that conduct to the silicon substrate
10
are produced as depicted in FIG.
31
. As described, the self-alignment method involves making contact holes through etching between wiring patterns while protecting these patterns with stopper films. The above method enables to manufacture desired contacts in a stable manner regardless of some errors in alignment between photoresist openings and wiring patterns.
According to the conventional method, however, part of the spaces between the silicon wires
14
are inevitably occupied by the nitride film side walls
18
. This reduces the widths of the contacts
24
formed between the silicon wires
14
, which makes it difficult to diminish the contact resistance between the contacts
24
and the silicon substrate
10
. In other words, a major problem with the conventional self-alignment method, despite its advantage in forming the contacts
24
stably, is a tendency to increase the contact resistance between the contacts
24
and the silicon substrate.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the previously-mentioned problems, and a general object of the present invention is to provide a novel and useful semiconductor device and a method for manufacturing the same.
A more specific object of the present invention is to provide a semiconductor device structured suitably to form contacts stably therein and to minimize contact resistance.
The above object of the present invention is achieved by a semiconductor device. The semiconductor device includes wiring patterns; nitride film top walls formed on top of the wiring patterns; nitride film side walls formed laterally to each of the wiring patterns; contacts which are each formed interposingly between the wiring patterns and which are isolated from the wiring patterns by the nitride film top walls and the nitride film side walls; and an oxide film formed under the wiring patterns. A bottom of the oxide film is lower than that of the nitride film side walls. A side edge surface of each of the oxide film is retracted away from a frontal edge of the corresponding nitride film side wall into the corresponding wiring pattern. Each of the contact extends into beneath of the corresponding nitride film side wall.
A further object of the present invention is to provide a method for manufacturing the semiconductor device targeted as the first object.
The above objects of the present invention is achieved by a method for manufacturing a semiconductor device. The method includes the steps for forming an oxide film on a semiconductor substrate; forming a wiring layer on the oxide film; forming a nitride film top wall layer on the wiring layer; forming wiring patterns and nitride film top walls by shaping the wiring layer and the nitride film top wall layer into suitable wiring pattern shape; forming nitride film side walls laterally to the wiring patterns and to the nitride film top walls; after depositing an interlayer oxide film, forming contact holes interposingly between the wiring patterns so that the nitride film top walls and the nitride film side walls will remain and that a side edge surface of the oxide film will be retracted from a frontal edge of the corresponding nitride film side wall into the corresponding wiring pattern; and forming contacts inside the contact holes.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5631484 (1997-05-01), Tsoi et al.
patent: 5656853 (1997-08-01), Ooishi
patent: 5808365 (1998-09-01), Mori
patent: 5886411 (1999-03-01), Kohyama
patent: 5936308 (1999-08-01), Rolfson
patent: 6028361 (2000-02-01), Ooishi
patent: 6057581 (2000-05-01), Doan
patent: 6087710 (2000-07-01), Eimori et al.
patent: 6091154 (2000-07-01), Ohkawa
patent: 6130482 (2000-10-01), Iio et al.
Shinkawata Hiroki
Terauchi Takashi
Cruz Lourdes
Lee Eddie C.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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