Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-04-13
2001-08-28
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000
Reexamination Certificate
active
06281537
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a highly integrated memory device, and more particularly to a ferroelectric capacitor memory device capable of improving an electrical interconnection between a lower electrode and an active region of a cell transistor.
2. Description of the Related Art
In general, a Pt film has been widely used as a lower electrode in highly integrated DRAM cells employing high dielectric materials as well as non-volatile memory device employing ferroelectric materials such as BST[Ba(Sr,Ti)O
3
].
FIG. 1
is a cross-sectional view of a conventional ferroelectric memory device having a Pt film as a lower electrode of a capacitor. As shown in
FIG. 1
, a capacitor in the conventional memory device is made up of a polysilicon plug
6
, a diffusion preventing film
7
and a lower electrode
8
such as a Pt film. Since the Pt film, which is commonly used as the lower electrode
8
, doesn't act as a barrier film preventing oxygen atoms from diffusing into its underlayer, the oxygen atoms are diffused into a diffusion preventing film
7
through the Pt film. In
FIG. 1
, unexplained reference numerals
1
denotes a semiconductor substrate,
2
field oxide film,
3
gate,
4
bit line,
5
interlayer insulating film, and
9
ferroelectric film.
A TiN/Ti film is widely used as the diffusion preventing film
7
. The barrier metal films such as TiN and Ti films and the polysilicon film for plug vigorously react on oxygen atoms from the dielectric film so that the oxidation takes place at a relatively low temperature of about 500° C. Accordingly, the electrical interconnection between the lower electrode and an active region of the transistor is broken down. With the increase of the deposition temperature of ferroelectric materials, this problem is getting more serious.
Particularly, in the case of ferroelectric materials, such as SrBi Ta O which is one of the prevailing materials for the ferroelectric capacitor, the temperature required in the deposition and crystallization is approximately 800° C. Therefore, in order to fabricate the ferroelectric memory device on the COB (capacitor on bit line) structure, it is most important to electrically connect the Pt lower electrode to the active region of the MOSFET.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved ferroelectric capacitor used in a memory device by providing reliable electrical interconnection between a lower electrode of the capacitor and an active region of transistor, and to provide a method for fabricating the same.
Another object of the present invention is to provide an ferroelectric capacitor to which excellent film properties of films are available, by achieving various selection of materials of a charge storage electrode.
In accordance with an aspect of the present invention, there is a provided a capacitor in a semiconductor device comprising: a first conducting film filling an opening which is formed in an interlayer insulating film, being in contact with an active region of a semiconductor; a stacked charge storage node including a second conducting film formed on the first conducting film and an interlayer insulating film, a first diffusion preventing film formed on the second diffusion film, a lower electrode film formed on the first diffusion preventing film, and a ferroelectric film formed on the lower electrode film; and a conducting spacer film formed on sidewalls of the lower electrode film, the first diffusion preventing film and the second conducting film.
In accordance with another aspect of the present invention, there is a provided a method for fabricating a capacitor in a semiconductor device comprising the steps of: forming an insulating film having an opening exposing an active region of a semiconductor substrate; forming a first conducting film for a contact plug filling the opening; forming a second conducting film, a first diffusion preventing film, a lower electrode film of the capacitor, a ferroelectric film and a second diffusion preventing film, in this order, on the insulating film and the first conducting film, so that a stacked charge storage node is formed; patterning the stacked charge storage node; forming a conducting spacer film electrically connecting the lower electrode film to the second conducting film on sidewalls of the stacked charge storage node, thereby forming a resulting structure; and forming a third diffusion preventing film on the resulting structure.
In accordance with further another aspect of the present invention, there is a provided a capacitor in a semiconductor device comprising: a first conducting film filling an opening which is formed in an interlayer insulating film, being in contact with an active region of a semiconductor; a first stacked structure including a second conducting film formed on the first conducting film and an interlayer insulating film, a first diffusion preventing film formed on the second conducting film, a lower electrode film formed on the first diffusion preventing film; a second stacked structure including a ferroelectric film formed on the lower electrode film and an upper electrode film formed on the ferroelectric film; an insulating spacer film formed on sidewall of the first stacked structure; a conducting spacer film formed on sidewall of the first stacked structure and the insulating spacer film; and a second diffusion preventing film formed on sidewalls of the insulating spacer film and the conducting spacer film.
In accordance with still another aspect of the present invention, there is a provided a method for fabricating a capacitor in a semiconductor device comprising the steps of: forming an insulating film having an opening exposing an active region of a semiconductor substrate; forming a first conducting film for a contact plug filling the opening; forming a second conducting film, a first diffusion preventing film, a lower electrode film of the capacitor, a ferroelectric film, an upper electrode film and an etching mask film, in this order, on the insulating film and the first conducting film; patterning the etching mask film, the upper electrode film and the ferroelectric film; forming an insulating spacer film on sidewalls of the etching mask film, the upper electrode film and the ferroelectric film; etching the lower electrode film, the first diffusion preventing film and the second conducting film, using the etching mask film and the insulating spacer film; forming an conducting spacer film on sidewalls of the etching mask film, the upper electrode film and the ferroelectric film; forming a conducting spacer film electrically connecting the lower electrode film to the second conducting film on sidewalls of the stacked charge storage node, thereby forming a resulting structure; and forming a second diffusion preventing film on the resulting structure.
REFERENCES:
patent: 5508953 (1996-04-01), Fukuda et al.
patent: 5572052 (1996-11-01), Kashihara et al.
patent: 5621606 (1997-04-01), Hwang
patent: 5798903 (1998-08-01), Dhote et al.
patent: 5825609 (1998-10-01), Andricacos et al.
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
Loke Steven
Nguyen Cuong Quang
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