Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-12-20
2001-08-28
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C714S724000
Reexamination Certificate
active
06281698
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an LSI testing apparatus and a timing calibration method for use therewith. More particularly, the invention relates to an LSI testing apparatus capable of completing its timing calibration in a short period of time and to a timing calibration method for allowing the LSI testing apparatus to finish its timing calibration quickly.
2. Description of the Background Art
FIG. 12
is a block diagram depicting a conventional LSI testing apparatus carrying out timing calibration based on a conventional timing calibration method. The conventional LSI testing apparatus
20
comprises a plurality of input/output (I/O) terminals
22
to be connected to the pins of an LSI (e.g., with pins
1
through N) under test. The testing apparatus
20
supplies the LSI to be tested with a clock signal, address signals and other signals via the I/O terminals
22
for desired tests.
The LSI testing apparatus
20
includes a controller
24
and a reference signal generator
26
. The reference signal generator
26
is connected to a waveform and timing generation circuit
28
furnished in corresponding relation to each of the I/O terminals
22
. Each waveform and timing generation circuit
28
is made up of two circuits. One circuit generates both a timing signal for varying the value of a signal output from the I/O terminal
22
and a timing signal for determining the value of a signal input to the I/O terminal
22
; another circuit determines the waveform of the output signal.
The waveform and timing generation circuit
28
is connected to a pin driver
32
via a skew circuit
30
. The skew circuit
30
is used to feed the pin driver
32
after a predetermined delay with a pulse signal generated by the waveform and timing generation circuit
28
. The pin driver
32
suitably amplifies the pulse signal, then supplying the amplified signal to the I/O terminal
22
.
Each I/O terminal
22
is connected to a decision circuit
38
via a relay
34
and a pin comparator
36
. The decision circuit
38
is connected to the waveform and timing generation circuit
28
via another skew circuit
40
. The skew circuit
40
is used to supply the decision circuit
38
after a predetermined delay with a timing signal generated by the waveform and timing generation circuit
28
. The decision circuit
38
determines the value of the signal input to the I/O terminal
22
synchronizing with the reception timing of the timing signal.
For the LSI testing apparatus to perform tests with high precision requires two preconditions: that signals output by the individual I/O terminals
22
should be consistent and in synchronism, and that signals input to the individual I/O terminals
22
should be consistently determined at an appropriate timing. Thus, the timings involved need to be calibrated from time to time to maintain the accuracy of the LSI testing apparatus.
The conventional LSI testing apparatus has its timing calibration conducted with a skew board
100
connected thereto as shown in FIG.
12
. The skew board
100
includes a relay matrix
102
made of hardware. The relay matrix
102
comprises relays corresponding to the plurality of I/O terminals
22
attached to the LSI testing apparatus. The relay matrix
102
is connected to a standard circuit
106
via a switching relay
104
and acts so that one of the I/O terminals
22
is allowed to conduct selectively to the switching relay
104
.
The standard circuit
106
has a standard driver
108
and a standard comparator
110
. The switching relay
104
allows the relay matrix
102
to connect with either the standard driver
108
or the standard comparator
110
. The standard driver
108
and standard comparator
110
operate in synchronism with a reference signal CLK generated by the reference signal generator
26
of the LSI testing apparatus
20
.
More specifically, the standard driver
108
, when connected to a particular I/O terminal
22
via the switching relay
104
and relay matrix
102
, supplies the I/O terminal
22
with a standard signal synchronized with the reference signal CLK. The standard comparator
110
, when connected to a specific I/O terminal
22
via the switching relay
104
and relay matrix
102
, determines the value of the signal output from the I/O terminal
22
in synchronism with the reference signal CLK.
The timing calibration of the conventional LSI testing apparatus is carried out with the standard circuit
106
of the skew board
100
connected individually to each of the I/O terminals
22
. When a single I/O terminal
22
is connected to the standard circuit
106
, two processes are performed: one for synchronizing the timings of signals output from a plurality of I/O terminals
22
, and another for synchronizing the timings in determining signals input to the individual I/O terminals
22
. Described below is an example in which a specific I/O terminal
22
(e.g., terminal
1
) is connected to the standard circuit
106
, i.e., where the relay matrix
102
connects the I/O terminal
22
in question to the switching relay
104
.
The process for synchronizing the output timings is performed while the switching relay
104
is being set to the standard comparator
110
. In that case, the signal output from the particular I/O terminal
22
is fed to the standard comparator
110
. The standard comparator
110
determines the value of the output signal in synchronized relation with the reference signal CLK. For timing calibration, the result of the determination above is used as a basis for adjusting the delay time of the skew circuit
30
in such a manner that the turning timing of the output signal is synchronized with a standard timing. When the process above has been carried out on all I/O terminals
22
, the turning timings of the output signals are synchronized on all terminals
22
.
The process for synchronizing the determining timings for the input signals is performed when the relay
34
corresponding to the I/O terminal
22
in question is closed, with the switching relay
104
set to the standard driver
108
. In that case, a standard signal generated by the standard driver
108
in synchronism with the reference signal CLK is fed as an input signal to the pin comparator
36
. The decision circuit
38
determines the value of the input signal on the basis of the timing signal supplied via the skew circuit
40
. For timing calibration, the delay time of the skew circuit
40
is adjusted in such a manner that the value of the standard signal is correctly determined. When the process above has been carried out on all I/O terminals
22
, the decision timings of the input signals are synchronized with respect to all terminals
22
.
The conventional method of timing calibration allows the LSI testing apparatus
20
to synchronize the turning timings of output signals and the decision timings of input signals on all I/O terminals
22
as described above. One disadvantage of the conventional timing calibration method is that the standard circuit
106
of the skew board
100
needs to be connected individually to all I/O terminals
22
, one at a time. In other words, the conventional calibration method requires processing time not less than N(number of pins) times of required time to complete the process for a single pin.
In recent years, as the number of the pins on LSIs to be tested becomes grater, more and more I/O terminals
22
have became required on the LSI testing apparatus
20
. That means it takes an inordinately long period of time to carry out the conventional method of timing calibration. In addition, the relay matrix
102
of the skew board
100
must be equipped with as many relays as the number of all I/O pins on the LSI testing apparatus
20
. Such a growing number of I/O pins on the testing apparatus
20
can make it increasingly difficult to handle the skew board
20
.
Timing calibration of the LSI testing apparatus
20
needs to be performed not only upon shipment or installation of the apparatus but also to provide against an
Funakura Teruhiko
Nakase Yasuhide
Nishimura Tomohiro
Sugimoto Masaru
Leroux E P
McDermott & Will & Emery
Metjahic Safet
Mitsubishi Denki & Kabushiki Kaisha
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