Practical air dielectric interconnections by post-processing...

Details Practical air dielectric interconnections by post-processing... Practical air dielectric interconnections by post-processing...

1999-06-24

2001-03-20

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S624000, C438S633000, C438S634000, C257S276000

Reexamination Certificate

active

06204165

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to the area of semiconductors and semiconductor processing and more particularly to methods and structures that provide low dielectric constant interconnects for integrated circuits.
2. Description of Related Art
Interconnect structures of integrated circuits (ICs) generally take the form of patterned metallization lines that are used to electrically interconnect devices and to provide interconnection with external circuitry. By way of example, IC devices may include metal oxide semiconductor (“MOS”) devices having diffused source and drain regions separated by channel regions, and gates located over the channel regions. In practice, an IC chip may include thousands or millions of devices such as MOS transistors.
Conventionally, a dielectric layer is deposited over the devices and via holes are formed through the dielectric layer to the devices below. After the via holes are etched through the dielectric layer, a metallization layer is deposited over the dielectric surface filling the via holes with metal vias. After the first metallization layer has been deposited, it is patterned to form interconnect metallization lines. AS is well known in the art, “patterning” may be accomplished by depositing a photoresist layer, selectively exposing the photoresist to light, developing the photoresist to form an etch mask, and etching the exposed metallization to pattern the metallization layer, and removing the etch mask. This process may then be repeated if additional layers of metallization lines are desired.
As IC technology scales, the performance of ultra large scale integrated (ULSI) chips is increasingly limited by the capacitance of the interconnects. The capacitance of the interconnects contributes to RC delay, AC power (CV
2
f) dissipation, and cross-talk. The use of air-gaps formed between metal lines during SiO
2
deposition has been shown to reduce the capacitance of tightly spaced interconnects by as much as 40% compared to homogeneous SiO
2
(see Shieh, B., et al.,
IEEE Electron Device Letters.,
19, no. 1, pp. 16-18.). This capacitance reduction is better than the reduction obtained using low-k materials such as polymers in a homogeneous scheme.
However, significant problems exist with present methods of forming air-gaps between interconnects. Many existing methods are specific only to Al or AlCu interconnects (see U.S. Pat. No. 5,798,559 issued to Bothra et al.) or require the development of new backend processes (see U.S. Pat Nos. 5,798,559 issued to Bothra et al. and 5,530,290 issued to Aitken et al.). Other methods of introducing air-gaps between interconnects are not compatible with chemical mechanical polishing (CMP) processes in multilevel interconnect systems because those methods can trap slurry in the gaps (see Shieh, B. P., et al., “Integration and Reliability Issues for Low Capacitance Air-Gap Interconnect Structures,” Proceedings of the International Interconnect Technology Conference, San Francisco, pp. 125-27, June 1998).
Therefore, it would be advantageous to have a method of introducing air-gaps between interconnects that does not require the development of new backend processes, that is compatible with many types of interconnect metals, and is compatible with CMP processes in multilevel interconnect systems.
SUMMARY OF THE INVENTION
The present invention provides a method of fabricating an integrated circuit having air-gaps between interconnect levels. In a preferred embodiment, an integrated circuit is partially fabricated. The partially fabricated integrated circuit includes a top layer, interconnect structures having a cladding layer, dielectric layers, and an etch stop layer resistant to certain first types of etchants. The top layer of the integrated circuit is etched with a second type of etchant. The dielectric layers are then etched with one of the first types of etchants until the etch stop layer is reached. Thus, portions of the interconnect structures are exposed to create interconnect islands surrounded by air. A cover is mechanically placed over the exposed interconnect islands to protect the integrated circuit from dust particles.


REFERENCES:
patent: 5530290 (1996-06-01), Aitken et al.
patent: 5798559 (1998-08-01), Bothra et al.
patent: 6017814 (2000-01-01), Grill et al.
patent: 6057224 (2000-01-01), Bothra et al.
patent: 6060381 (2000-05-01), Nakagawara et al.
Shieh et al.; Integration and Reliability Issues For Low Capacitance Air-Gap Interconnect Structures; pp. 98-125—98-127.

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