Methods of performing sector erase operations on...

Details Methods of performing sector erase operations on... Methods of performing sector erase operations on...

2000-02-18

2001-04-24

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240, C365S185290

Reexamination Certificate

active

06222772

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to electrically erasable and programmable nonvolatile semiconductor memory devices and methods of erasing the same memory devices.
BACKGROUND OF THE INVENTION
Semiconductor memory device for storing data can typically be categorized as either volatile memory devices or non-volatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted, in contrast to this, non-volatile memory devices retain their stored data even when their power supplies are interrupted. Thus, non-volatile memory devices are widely used in applications where the possibility of power supply interruption is present.
Conventional non-volatile memory devices include a type of electrically erasable programmable read only memory (EEPROM) device having transistors as memory cells, which is usually referred to as a flash memory device. With reference to
FIG. 1
, a typical flash memory cell includes spaced source and drain regions
3
and
4
of first conductivity type (e.g., N-type) in a semiconductor substrate or bulk
2
of second conductivity type (e.g., P-type); a channel region at a face of the substrate
2
, between the spaced source and drain regions
3
and
4
; an electrically floating gate
6
for storing charge carriers when the cell is programmed; and a control gate
8
which overlies the floating gate
6
, opposite the channel region. The floating gate
6
is completely surrounded by insulations
7
and
9
.
Operation of a flash EEPROM device is typically divided into three modes including programming, erasing and reading.
A flash cell is typically programmed by hot electron injection from its bulk (or substrate) to its floating gate. To induce such an effect, it is necessary to supply the control gate and drain of the cell with program voltages (e.g., about 8-12 V for the control gate, and 5-6 V for the drain) which are higher than read voltages (e.g., 4-5 V for the control gate, and about 1 V for the drain) for reading data out of the cell, with its source and bulk grounded.
During the programming mode, the floating gate accumulates the hot electrons and traps the accumulated electrons. The accumulation of a large quantity of trapped electrons in the floating gate causes the effective threshold voltage of the cell transistor to increase (e.g., about 6-7 V). If this increase is sufficiently large, the cell transistor will remain in a non-conductive state when the read voltages are applied thereto during a read operation. In this programmed state, the cell may be said to be storing a logic 1 (“OFF cell”). Such a programmed state of the cell remains even when power supply is interrupted.
Erasing a flash cell transistor is to remove the charge accumulated in its floating gate. The erase operation of a flash cell can be carried out, for example, by applying a negative high voltage (e.g., about −10 V) to its control gate and an appropriate positive voltage (e.g., 5-6 V) to its bulk, having its source and drain floated. This causes cold electron tunneling (i.e., Fowler-Nordheim tunneling) through the thin insulation (e.g., below 100 Å) between the floating gate and the bulk, leading to a decrease in the threshold voltage of the cell transistor (e.g., 1-3 V). The erase voltages may be applied to the cell until it is erased below a maximum threshold voltage acceptable. Accordingly, if a flash cell has been erased, it will heavily conduct. In this case, the cell may be said to be storing a logic 0 (“ON cell”). Thus, by monitoring the bit line current, the programmed or erased state (i.e., 1 or 0) of the cell can be determined.
Meanwhile, most of the state-of-the-art flash memory devices of high density adopt a segmented cell array architecture. Namely, bulk (i.e., substrate) and cell array are divided into a number of sectors. This architecture causes all of the cells within a sector of, for example, 16 k or 64 k bytes capacity to be erased simultaneously.
In such a sector erase operation, due to threshold uniformity, manufacturing condition, amount of use, temperature, etc., one or more cells within the sector may be erased below a minimum acceptable threshold voltage (e.g., 1 V), as shown in FIG.
2
. This is because too much charge is removed from the floating gates of the cells, making the cells “depletion-like”. The cell erased below the minimum threshold is commonly referred to as being “overerased”. An overerased cell may induce a leakage current on its associated bit-line, thereby causing errors when reading other cells on the same bit-line.
One solution to this problem is to repair the overerased cells, The method of curing the overerased cells is an iterative process utilizing overerase verification and low-voltage level programming.
In general, the sector erase operation of flash EEPROM devices is carried out as in the following. First, all of the memory cells within a sector are sequentially programmed to narrow their threshold distribution. All the cells of the sector are then erased at a time (hereinafter referred to as “negative gate bulk erase operation”). Thereafter, repair operation begins with selecting a row (i.e., a word-line) and examining the cells on the selected row one by one along columns (i.e., bit-lines) to determine whether there are overerased cells. This procedure is commonly referred to as overerase verification. In this verification, a cell is identified as overerased when it conducts current in excess of the current expected at the lowest threshold voltage (e.g., 1 V). Once identified as overerased, a cell is programmed with low-level repair voltages (e.g., 2-5 V to the control gate, 6-9 V to the drain, and 0 V to the source and bulk). Repair of the remaining cells on other rows is performed in the same fashion.
FIG. 3
is a flowchart of a conventional algorithm for sector erasing of flash memory devices. When a sector erase command is issued at step S
100
, a sector erasing begins in step S
105
by resetting an address counter AC and a pulse counter PC to zero. The address counter AC counts addresses of all the memory cells in a sector to be erased. The pulse counter PC is used to number the negative gate bulk erase operations in a sector erase operation. In step S
110
, a negative gate bulk erasing is executed, during which the cells have their control gates applied with a negative high voltage (e.g., about −10 V), their bulk applied with an appropriate positive voltage (e.g., 5-6 V), and their sources and drains floated. Thereafter, flow proceeds to step S
115
, wherein it is sequentially verified whether each of the erased cells has its threshold voltage below a maximum acceptable threshold voltage (e.g., 3 V). In this erase verification, gate of the selected cell is supplied with an appropriate positive voltage for a given time such that a data bit of the selected cell is read out. It is then determined whether or not the data bit equals logic 0, that is, the selected cell is an ON cell, at step S
120
. If so, flow advances to step S
125
wherein it is checked whether the address counter AC designates a maximum address ACmax (i.e., the address of the last cell), and if not, flow proceeds to step S
135
wherein the pulse counter PC points out a maximum number PCmax of the negative gate bulk erase operations in the sector erase operation. In step S
125
, if not, flow continues back to step S
115
via step S
130
wherein the value of address counter AC is increased from AC to AC+1, and if so, flow proceeds to step S
150
wherein the sector erasing is terminated, reaching the conclusion that the sector is successfully erased (i.e., “erase pass”). In step S
135
, if not, flow continues back to step S
110
via step S
140
wherein the value of pulse counter PC is increased from PC to PC+1, and if so, the sector erasing is also terminated at step S
145
, judging the sector not to be erased successfully (i.e., “erase fail”).
In the above-described erasing method, however, if there exist one or more defective cells (to lower manufacturing cost as much

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