Electrical computers and digital data processing systems: input/ – Interrupt processing
Utility Patent
1997-09-30
2001-01-02
Follansbee, John A. (Department: 2781)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S262000, C712S244000
Utility Patent
active
06170033
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to handling interrupts. More particularly, the application relates to a method and apparatus to enable an interrupt handler to operate on errors that would normally be handled by a non-maskable interrupt (NMI) handler.
2. Description of Related Art
Processing circuits have traditionally generated non-maskable interrupts (NMI) and forwarded the NMI to a NMI handler. One event which results in a NMI is an input/output error (I/O check) which is asserted when a problem occurs on a parallel port transfer. The I/O check error is an Industry Standard Architecture (ISA) error. A second cause of NMIs is the assertion of a Peripheral Component Interface (PCI) system error, called “SERR#”. One event which causes SERR# is typically a problem with error correcting code memory. Either an asserted SERR# or an asserted I/O check error may cause processing circuitry to generate a non-maskable interrupt error.
Processing circuits traditionally include a set of gates to combine causes of NMIs into one NMI signal line to a host CPU. In one embodiment of the prior art, the gates combine causes of NMIs with enables to generate a NMI signal. The interrupt signal is typically input into a latch. A clock signal times the output of the latch.
Current systems typically avoid asserting a non-maskable interrupt because of the disruptive nature of such interrupts. NMIs are not scheduled like most other interrupts, instead NMIs are handled immediately. The resulting disturbance in instruction flow has caused many operating system vendors to write operating systems which do not handle NMI interrupts. Instead, received NMIs cause a system reset which is disruptive to the system operation.
In order to avoid system resets which result when the NMI occurs, the causes of interrupts may be transmitted to a separate set of routing logic which generates a system management interrupt (SMI). The SMI is then subsequently transferred to BIOS. BIOS typically handles SMI without resetting the system.
However, asserting SMI is not without problems. An asserted SMI typically transfers control of the system to the BIOS resulting in disruption of operating systems functions. Thus, many operating systems do not handle SMI well because operating systems cannot schedule tasks during assertion of SMI.
Thus, a system is needed for generating alternative interrupts which indicate a NMI problem but are not as disruptive as the assertion of NMI. In the preferred embodiment, the system will utilize SCI (System Control Interrupt), a new interrupt introduced as part of the Advance Control Power Interface (ACPI). The ACPI is an open industry specification co-developed by Intel Corporation, Microsoft Corporation and Toshiba. A copy of the Advanced Configuration and Power Interface Specification, Revision 1.0 of Dec. 22, 1996 is available at internet web site www.teleport.com/~acpi/tech.htm#spec.
SUMMARY OF THE INVENTION
A system which forwards causes of non-maskable interrupts is described. The system includes a determining circuit to determine whether an interrupt handler can handle an alternative interrupt. An output of the determining circuit is output to a switch which forwards causes of NMI to a first line when the determining circuit determines that the interrupt handler can handle alternative interrupts. The switch forwards causes of NMI to a second line when the determining circuit determines that the interrupt handler cannot handle alternative interrupts.
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Blakely , Sokoloff, Taylor & Zafman LLP
Follansbee John A.
Intel Corporation
Vo Tim T.
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