Method for preventing polycide line deformation by polycide hard

Details Method for preventing polycide line deformation by polycide hard Method for preventing polycide line deformation by polycide hard

1996-10-18

1999-08-31

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438625, 438630, 438632, 438646, 438647, H01L 2144

Patent

active

059465964

ABSTRACT:
The present invention provides a method for preventing a polycide line situated between two dielectric layers from deformation during a reflow process for one of the dielectric layers by annealing the polycide line and thereby increasing its hardness prior to the reflow process being conducted. The annealing process can be carried out either before or after the polycide line is formed at an annealing temperature in the range between about 700.degree. C. and about 1000.degree. C. in a furnace or by a rapid thermal process.

REFERENCES:
patent: 5084412 (1992-01-01), Nakasaki
patent: 5731225 (1998-03-01), Yamamori

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