Method and apparatus for distributing interrupts in a symmetric

Electrical computers and digital data processing systems: input/ – Interrupt processing

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710261, 710262, 710263, 710264, 710265, 710266, 710113, 395733, 395734, 395737, 395739, 395293, G06F 1300

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active

059448091

ABSTRACT:
A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. One of the at least one COPICs functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.

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