Stress reduction for non-volatile memory cell

Details Stress reduction for non-volatile memory cell Stress reduction for non-volatile memory cell

1994-01-19

1995-07-18

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

365184, 365218, G11C 700

Patent

active

054348153

ABSTRACT:
Non-volatile semiconductor core memory performance is enhanced by reduced stress on core memory cells. Stress is reduced by selectable application of bias voltages to the sense line under control of the word line. The word line is connected to an inverting device in turn connected to a transistor effective for grounding the gate of a variable threshold programmable transistor in the memory cell. Power down of the word line is reflected in synchronous power-down of the sense line. Additionally, with power down, the sense amplifier for the particular core memory cell is disconnected from a master latch circuit, which in turn is connected to a slave latch circuit for applying the previous sense amplifier output to an input/output buffer, in order to secure the data sensed in core memory during read operation. The invention further permits reduced word line voltages during erase operation on the sense line and the variable threshold programmable transistor.

REFERENCES:
patent: 4179626 (1979-12-01), Oehler

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