Field effect transistor with offset region

Details Field effect transistor with offset region Field effect transistor with offset region

1992-03-19

1994-05-10

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257339, H01L 2976, H01L 2994

Patent

active

053110510

ABSTRACT:
In a high breakdown voltage MOSFET having an offset region consisting of a low concentration impurity layer with the same conductivity type as that of a drain region between a channel region and the drain region, an impurity layer with conductivity type opposite to that of the drain region is formed on the surface of the offset region. With such a constitution, even for the case when the energy levels generated in the interface of silicon/oxide film under the environment of exposure to radiations act as the scattering centers, the drain current will not be affected by the levels. Further, the reliability of the high breakdown voltage MOSFET can be improved markedly, by suppressing the deterioration in the charge mobility due to generation of the interface levels and the accompanying reduction in the drain current.

REFERENCES:
patent: 4300150 (1981-11-01), Colak
patent: 4811075 (1989-03-01), Eklund
patent: 4823173 (1989-04-01), Beasom
patent: 5023678 (1991-06-01), Kinzer
patent: 5072268 (1991-12-01), Rumennik
patent: 5089871 (1992-02-01), Fujihara
patent: 5162883 (1992-11-01), Fujihara
"Device Design of an Ion Implanted High Voltage MOSFET", I. Yoshida, et al., Supplement to the Journal of the Japan Society of Applied Physics, vol. 44, 1975, pp. 249-255.

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