Two-layer polysilicon process for forming a stacked DRAM capacit

Details Two-layer polysilicon process for forming a stacked DRAM capacit Two-layer polysilicon process for forming a stacked DRAM capacit

1996-04-22

1997-07-08

Tsai, Jey

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

056460619

ABSTRACT:
A method for forming a lower plate of a STC DRAM storage capacitor and its contact to the source diffusion of the transfer MOSFET is described which reduces the risk of dopant encroachment into shallow active device regions within a silicon wafer, without sacrificing contact stability and integrity. In addition, the storage capacitor does not suffer appreciable voltage degradation caused by carrier depletion in its lower plate. This is accomplished by depositing a thick, in-situ doped first layer of polysilicon over an insulating layer which covers the semiconductor device. Next, a contact opening is made and a thin layer of undoped polysilicon is deposited to complete the lower plate. In one embodiment this layer is not subsequently doped by ion implantation but receives an infusion of dopant from the first polysilicon layer during an annealing step. The annealing step affords a stable, ohmic contact with good capacitive-voltage characteristics. In another embodiment a shallow oblique implant is introduced into the thin polysilicon layer to further improve the capacitive characteristics.

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