Computer system and method for obtaining memory check points and

Details Computer system and method for obtaining memory check points and Computer system and method for obtaining memory check points and

1996-06-18

1998-12-01

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

39518213, 395569, 711143, G06F 1300, G06F 1216

Patent

active

058453261

ABSTRACT:
A computer system including a plurality of processors and a copyback cache memory and a method for periodically obtaining a first and second phase memory checkpoints and recovering from faults using the checkpoints, are disclosed. The computer system has cache flush hardware for executing a cache flush operation independently of the processors, including cache flush starters for starting the cache flush hardware, and cache flush end detectors for detecting the end of the cache flush operation. During a first phase checkpoint, the cache flush and normal data processing are done in parallel. When the cache flush end detectors detect the termination of the cache flush hardware, the processors suspend normal data processing, and a second checkpoint step is executed in which the processors save the context of the processors in the main memory and the cache flush hardware is invoked again so that dirty data in the cache memory is written back in to the main memory.

REFERENCES:
patent: 4740969 (1988-04-01), Fremont
patent: 5418916 (1995-05-01), Hall et al.
patent: 5659721 (1997-08-01), Shen et al.
Wu et al., "Error Recovery in Shared Memory Multiprocessors Using Private Caches," IEEE, vol. 1, No. 2 (Apr. 1, 1990).

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