Video subsystem power management apparatus and method

Details Video subsystem power management apparatus and method Video subsystem power management apparatus and method

1996-04-10

1997-04-08

Harvey, Jack B.

G06F 1300

Patent

active

056197071

ABSTRACT:
Power is conserved in a video subsystem by inactivating a pixel clock (PCLK) and reducing frequency of a memory clock (MCLK) responsive to an indication of user inactivity. The inactivation of PCLK reduces the power consumed in the RAMDAC, frame buffer, phase lock loop (PLL) clock circuit, and to a smaller extent, the video controller. Reducing the frequency of MCLK conserves power in the video controller and the PLL, while maintaining the integrity of the data in the frame buffer. Significant power savings can be accomplished with minimal BIOS or video controller programming and minimal transfer of state information prior to power-down.

REFERENCES:
patent: 5167024 (1992-11-01), Smith et al.
patent: 5321806 (1994-06-01), Meinerth et al.
patent: 5402148 (1995-03-01), Post et al.
patent: 5408639 (1995-04-01), Gulick et al.

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