Fishing – trapping – and vermin destroying
Patent
1993-11-23
1996-02-13
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437189, 437200, 437 43, H01L 21336
Patent
active
054911001
ABSTRACT:
A method of manufacturing and a structure of a semiconductor device is disclosed whereby a gate insulating layer, a polycrystalline silicon layer, a tungsten silicide layer and a first insulating layer are formed on a semiconductor substrate. Gates are formed by the removal of the layers by dry etching, wherein the etch rate of the tungsten silicide layer is faster than the other layers, thereby forming an undercut region in the tungsten silicide layer. A second insulating layer is formed on the surface of the resultant structure to form spacers, and a contact window is formed between the gates via an etching process. The second insulating layer portion which forms the spacers need not be thick to prevent etching of the gates when forming the contact window, therefore good step coverage is achieved and reliability of the device is increased.
REFERENCES:
patent: 4740484 (1988-04-01), Norstrom
patent: 4935380 (1990-06-01), Okumura
patent: 4978637 (1990-12-01), Liou
patent: 5089863 (1992-02-01), Satoh et al.
patent: 5262352 (1993-11-01), Woo et al.
Lee Yong H.
Seo Young W.
Chaudhuri Olik
Donohoe Charles R.
Mulpuri S.
Samsung Electronics Co,. Ltd.
Whitt Stephen R.
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