High speed low pin count bus interface

Details High speed low pin count bus interface High speed low pin count bus interface

1987-05-01

1988-09-27

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307448, 307473, 307243, H03K 1716, H03K 19017, H03K 19092

Patent

active

047744227

ABSTRACT:
Bus interface apparatus is provided to drive a high speed bus with two nonoverlapping clock signals. The apparatus takes advantage of the inherent bus capacitance which will temporarily hold data signals placed on the bus by using bus interface circuitry having high input and output impedances. That circuitry can thus be activated by coincident signals.

REFERENCES:
patent: 3585399 (1971-06-01), Andrews, Jr.
patent: 3912948 (1975-10-01), Buchanan
patent: 4347600 (1982-08-01), Abbott et al.
patent: 4376998 (1983-03-01), Abbott et al.
patent: 4408333 (1983-10-01), Fujii
patent: 4409671 (1983-10-01), Daniels et al.
patent: 4414480 (1983-11-01), Zasio
patent: 4417163 (1983-11-01), Otsuki et al.
patent: 4471243 (1984-09-01), Isham
patent: 4486753 (1984-12-01), Saeki et al.
patent: 4542305 (1917-09-01), Blauschild
patent: 4558237 (1985-10-01), Rabe et al.
patent: 4587441 (1986-05-01), Torelli
patent: 4608504 (1986-08-01), Yamamoto
patent: 4625126 (1986-11-01), Tinker
patent: 4645947 (1987-02-01), Prak

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