Error correction circuit using a design based on a neural networ

Details Error correction circuit using a design based on a neural networ Error correction circuit using a design based on a neural networ

1990-07-09

1993-01-05

Beausoliel, Robert W.

Excavating

395 27, G06F 1108

Patent

active

051777460

ABSTRACT:
An error correction circuit is provided which uses NMOS and PMOS synapses to form neural network type responses to a coded multi-bit input. Use of MOS technology logic in error correction circuits allows such devices to be easily interfaced with other like technology circuits without the need to use distinct interface logic as with conventional error correction circuitry.

REFERENCES:
patent: 4988891 (1991-01-01), Mashiko
patent: 5034918 (1991-07-01), Jeong
patent: 5047655 (1991-09-01), Chambost et al.
Kwon et al., Implementation of a Programmable Artificial Neuron Using Discrete Logic, 1989 (no month available).
Eberhardt et al., Design of Parallel Hardware Neural Network Systems From Custom Analog VLSI `Building Block` Chips, Jun. 1989.
Bloomer et al., A Preprogrammed Artificial Neural Network in Signal Processing of IEEE Custon IC, May 1990.
Graf et al., VLSI Implementation of a Neural Network Model, 1988 (no month available).

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