Method and apparatus for managing multiple lock indicators in a

Details Method and apparatus for managing multiple lock indicators in a Method and apparatus for managing multiple lock indicators in a

1989-06-28

1991-11-26

Eng, David Y.

Boots, shoes, and leggings

364240, 3642408, 3642409, 364DIG1, G06F 1338, G06F 1342

Patent

active

050687816

ABSTRACT:
A computer system having multiple processors interconnected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to a memory or I/O node. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processes in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue. The memory obtains access to the pended bus through an arbitration process and transmits a response message including the contents of the memory location specified in the interlock read command at an unspecified time after initiation of the interlock read command. A subsequent interlock read command from the processor to the same memory location will result in a denial of access to the specified location and in the generation of a second type of response message by the memory which indicates that the specified location is locked.

REFERENCES:
patent: 3398405 (1968-08-01), Carlson et al.
patent: 3528061 (1970-09-01), Zurcher, Jr.
patent: 3665484 (1972-05-01), Nanba
patent: 3761883 (1973-09-01), Alvarez et al.
patent: 3916384 (1975-10-01), Fleming et al.
patent: 3993981 (1976-11-01), Cassarino et al.
patent: 3997875 (1976-12-01), Broeren
patent: 4000485 (1976-12-01), Barlow et al.
patent: 4050059 (1977-09-01), Williams et al.
patent: 4055851 (1977-10-01), Jenkins et al.
patent: 4075692 (1978-02-01), Sorenson et al.
patent: 4099243 (1978-07-01), Palumbo
patent: 4161778 (1979-07-01), Getson et al.
patent: 4214304 (1980-07-01), Shimizu et al.
patent: 4296466 (1981-10-01), Guyer et al.
patent: 4313161 (1982-01-01), Hardin et al.
patent: 4315310 (1982-02-01), Bayliss et al.
patent: 4384322 (1983-05-01), Bruce et al.
patent: 4407016 (1983-09-01), Bayliss et al.
patent: 4480307 (1984-10-01), Budde et al.
patent: 4481573 (1984-11-01), Fukunaga et al.
patent: 4574350 (1986-03-01), Starr
patent: 4587609 (1986-05-01), Boudreau et al.
patent: 4621318 (1986-11-01), Maeda
patent: 4698753 (1987-10-01), Hubbins et al.
patent: 4706190 (1987-11-01), Bomba et al.
patent: 4709326 (1987-11-01), Robinson

Affiliated with

Also associated with

Rating

Method and apparatus for managing multiple lock indicators in a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for managing multiple lock indicators in a , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for managing multiple lock indicators in a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2389529