Method for forming a high valued resistive load element and low

Details Method for forming a high valued resistive load element and low Method for forming a high valued resistive load element and low

1990-05-31

1991-11-26

Hearn, Brian

Fishing, trapping, and vermin destroying

437 47, 437 52, 437200, 437918, 148DIG136, H01L 21283

Patent

active

050682016

ABSTRACT:
A method for forming integrated circuit structures includes the formation of high-value resistive elements and low resistance interconnect in a single polycrystalline layer. In one embodiment, interconnect regions of the polycrystalline silicon layer are masked, and resistive element regions are partially oxidized to reduce the thickness of the polycrystalline layer in such regions. Resistivity of the interconnect regions may then be reduced by implanting a high level of impurities in them, or by forming a refractory metal silicide layer over the interconnect regions. The oxide formed over the resistive elements during the oxidation thereof protects them from either of the following process steps, so that no masking is required. In an alternative embodiment, silicidation of the interconnect regions of the polycrystalline silicon layer may be performed without the prior local oxidations of the resistive element regions.

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patent: 4916507 (1990-04-01), Boudou et al.
patent: 4948747 (1990-08-01), Pfiester
patent: 4961103 (1990-10-01), Saitoh et al.
patent: 4965214 (1990-10-01), Choi et al.
patent: 4968645 (1990-11-01), Baldi et al.

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