Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-03-02
1999-12-28
Abraham, Fetsum
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257298, 257308, 257311, 257336, 257296, H01L 29788
Patent
active
060085177
ABSTRACT:
The memory cell in the present invention is formed in a semiconductor substrate with isolations formed upon to separate cells. The cell has an oxide layer between the isolations. The oxide layer includes a pad oxide member, two tunnel oxide members, and two insulating oxide members. The two insulating oxide members are separated from both sides of the pad oxide member by the two tunnel oxide members. The two tunnel oxide members are thinner than the pad oxide member and the two insulating oxide members. The memory cell has a doped junction region in the semiconductor substrate under the two insulating oxide members and the two tunnel oxide members. The cell also has a first conductive layer over the oxide layer and a dielectric layer over the first conductive layer. A second conductive layer is located over the dielectric layer. In addition, the memory cell can further include an undoped hemispherical grain (HSG) silicon film between the first conductive layer and the dielectric layer. Thus the surface area of the first conductive as a floating gate can be greatly raised to increase the capacitive-coupling ratio.
REFERENCES:
Albert Bergemont et al., Low Voltage NVG.TM.: A New High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications Applications, IEEE Transactions on Electron Devices, vol. 43, No. 9, Sep. 1996, pp. 1510-1517.
H. Shirai et al., A 0.54.mu.m.sup.2 Self-Aligned, HSG Floating Gate Cell (SAHF Cell) for 256Mbit Flash Memories, 1995 IEEE,pp. 653-656.
Yosiaki S. Hisamune et al., A High capacitive-Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories, 1993 IEEE, pp. 19-22.
Shye Lin Wu et al., Characterization of Thin Textured Tunnel Oxide Prepared by Thermal Oxidation of Thin Polysilicon Film on Silicon, IEEE Transactions on Electron Devices, vol. 43, No. 2, Feb. 1996, pp. 287-294.
Takashi Hori et al., A MOSFET with Si-implanted Gate-SiO.sub.2 Insulator for Nonvolatile Memory Applications, 1992 IEEE, pp. 469-472.
Abraham Fetsum
Texas Instruments - Acer Incorporated
LandOfFree
High density and low power flash memories with a high capacitive does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High density and low power flash memories with a high capacitive, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density and low power flash memories with a high capacitive will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2383982