Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Patent
1998-03-25
1999-12-28
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
438211, 438248, 438257, 438259, 438262, 438263, 438 27, H01L 21338, H01L 218242
Patent
active
060080795
ABSTRACT:
The present invention proposes a method for fabricating a high-density shallow trench contactless nonvolatile memory. First, a stacked pad oxide/silicon nitride layer is deposited on the substrate and the buried bit line region is defined by a photoresist. An anisotropic etching follows to etch the silicon layer and then the n+ impurity ions are implanted to form the source and drain. After stripping the photoresist, a high temperature steam oxidation process is used to grow a thick field oxide, and the doped ions are active and driven in to form the buried bit lines simultaneously. The silicon nitride layer and the pad oxide layer are then removed, and the silicon substrate is recessed by using the field oxide as an etching mask. After rounding the trench corners by using thermal oxidation and etching back processes, a thin silicon oxy-nitride film is regrown. An in-situ doped polysilicon film is deposited to refill the trench region and then etch back by using a CMP process to form the floating gates. Next, the interpoly dielectric such as ultra-thin ONO film, and, the control gate formed of n+ doped polysilicon film, are sequentially built. After the word lines are defined, the nonvolatile memory is thus finished.
REFERENCES:
patent: 5423973 (1995-06-01), Hong
patent: 5480819 (1996-01-01), Huang
patent: 5521110 (1996-05-01), Gill
patent: 5554568 (1996-09-01), Wen
patent: 5661055 (1997-08-01), Hsu et al.
patent: 5680345 (1997-10-01), Hsu et al.
patent: 5744847 (1998-04-01), Wen
patent: 5763310 (1998-06-01), Gardner
patent: 5923977 (1999-07-01), Ahmad et al.
Fiegna et al. "Scaling the MOS trnasistor below 0.1 microns: Methodology, device structures and technology requirements," IEEE Transactions on Electron Devices, vol. 41, No. 6, pp. 941-951, 1994.
Albert Bergemont et al., Low Voltage NVG.TM.: A New High Performance 3 V/5 Flash Technology for Portable Computing and Telecommunications Applications, IEEE Transactions on Electron Devices, vol. 43, No. 9, Sep. 1996, pp. 1510-1517.
Paul-Henri Bricout et al., Short-Channel Effect Immunity and Current Capability of Sub-0.1-Micron MOSFET's Using a Recessed Channel, IEEE Transactions on Electron Devices, vol. 43, No. 8, Aug. 1996, pp. 1251-1255.
H. Shirai et al., A 0.54.mu.m.sup.2 Self-Aligned, HSG Floating Gate Cell (SAHF Cell) for 256Mbit Flash Memories, 1995 IEEE, pp. 653-656.
Hack Jonathan
Niebling John F.
Texas Instruments--Acer Incorporated
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