Method for controlling clock frequency of a digital logic semico

Details Method for controlling clock frequency of a digital logic semico Method for controlling clock frequency of a digital logic semico

1994-11-09

1996-01-02

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 32, 326 9, 326101, H03K 700, H03K 1900

Patent

active

054812100

ABSTRACT:
A method for operating a digital logic semiconductor component, wherein: the logic semiconductor component is operated in several operational modes at respective fixed clock cycles depending on environmental temperatures; each operational mode is allocated a respective clock cycle with, in each case, a different clock frequency; each operational mode is allocated a respective temperature-dependent limit value with, in each case, a different limit temperature which when reached causes a change of operational mode to occur; and, when changing to an operational mode with a higher limit temperature, the clock frequency is reduced, and when changing to an operational mode with a lower limit temperature, the clock frequency is increased.

REFERENCES:
patent: 3725789 (1973-04-01), Mager
patent: 3835458 (1974-09-01), Mrazek
patent: 3938316 (1976-02-01), Morokawa et al.
patent: 4710648 (1987-12-01), Hanamura et al.

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