Semiconductor memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257390, H01L 2348, H01L 2940, H01L 2944, H01L 2952

Patent

active

053249755

ABSTRACT:
For increasing pattern density of cell regions in a semiconductor memory device including an array of dynamic memory cells, the cell regions for cell transistor pairs are provided in a semiconductor substrate so as to be crossed by one desired bit line and two word lines adjacent thereto, and the patterns of cell regions have a same direction. Contacts for electrically connecting each bit line to common regions of cell transistor pairs are provided on respective bit lines every desired pitch at positions where each bit line intersects with cell regions. These contacts of adjacent bit lines are successively shifted in a bit line direction by approximately 1/2.sup.n (n is natural numbers greater than or equal to 2) pitch.

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Kimura et al., "A New Stacked Capacitor DRAM Cell Characterized by a Storage Capacitor on a Bit-line Structure", International Electron Devices Meeting (San Francisco, CA. Dec. 11-14, 1988) at 596-99.
Aoki et al., "A 1.5V DRAM for Battery-Based Applications", IEEE Int'l Solid-State Circuits Conf. (Feb. 17, 1989) at 238-40.

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