Semiconductor SRAM with trench transistors

Details Semiconductor SRAM with trench transistors Semiconductor SRAM with trench transistors

1993-05-03

1994-06-28

Limanek, Robert

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257393, 257903, H01L 2910

Patent

active

053249739

ABSTRACT:
A semiconductor memory cell (10) includes vertically disposed MOS pass transistors (32, 34) and MOS inverters (12, 14) contained in trench structures in a semiconductor substrate (11). An MOS inverter (12) has a toroidal shared-gate electrode (48) overlying the wall surface of a first trench (36). A pass transistor (32) has a gate electrode (84) in a third trench (40). A first buried drain region (62) resides in the substrate (11) adjacent to the first trench (36), and is located a first distance from the substrate surface. A second buried drain region (64) resides in the substrate (11) adjacent to the second trench (32), and is located a second distance from the substrate surface. The inverter (12) and the pass transistor (32) are electrically coupled by the first and second buried layers (62, 64). The channel length (90) of the driver transistor (16) in the inverter (12) and the pass transistor (32) is determined by the first and second distances, respectively. Accordingly, the cell ratio of the memory cell (10) (ratio of W/L values) is also determined by the differential depth of the first and second buried drain regions (62, 64).

REFERENCES:
patent: 4881105 (1989-11-01), Davari et al.
patent: 4890144 (1989-12-01), Teng et al.
patent: 4920397 (1990-04-01), Ishijima
patent: 5016070 (1991-05-01), Sundaresan
patent: 5122848 (1992-06-01), Lee et al.
patent: 5231043 (1993-07-01), Chan et al.
R. Eklund, et al. "A 0.5 Micron BiCMOS Technology for Logic and 4Mbit-class SRAM's" IEEE-IEDM, 1989, 425-428.
K. Sunouchi, et al., "A Surrounding Gate Transitor (SGT) Cell for 64/256Mbit DRAMs" IEEE-IEDM, 1989, 23-26.

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