Memory architecture and devices, systems and methods utilizing t

Details Memory architecture and devices, systems and methods utilizing t Memory architecture and devices, systems and methods utilizing t

1995-09-21

1996-10-22

Nelms, David C.

Static information storage and retrieval

Read/write circuit

With shift register

365239, 365240, 36523003, 36523005, G11C 700

Patent

active

055684319

ABSTRACT:
A memory 200 is provided including a plurality of arrays 202 of memory cells 203. A plurality of registers 211 are also provided, each register 211 for exchanging parallel bits of data with a corresponding one of the arrays 202. Data transfer circuitry 210, 213 is included for transferring parallel bits of data from any selected one of the arrays 202 through the corresponding register 211 to any other selected one of the arrays 202 through the corresponding register 211.

REFERENCES:
patent: 4987559 (1991-01-01), Miyauchi et al.
patent: 5161221 (1992-01-01), Van Nostrand
patent: 5200925 (1993-03-01), Morooka
patent: 5270973 (1993-12-01), Guiliemond et al.
patent: 5377154 (1994-12-01), Taku sugi
patent: 5463591 (1995-10-01), Aimoto et al.
patent: 5473566 (1995-12-01), Rao et al.

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