Non-volatile semiconductor memory device and data erasing method

Details Non-volatile semiconductor memory device and data erasing method Non-volatile semiconductor memory device and data erasing method

1995-07-27

1996-10-22

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular biasing

36518522, G11C 1134

Patent

active

055684190

ABSTRACT:
A memory cell array has a plurality of memory cells formed of EEPROM cells arranged in a matrix form. Data in the memory cells is flash-erased, and after this, word lines other than a selected word line are set to a negative potential and erasing verification for detecting an insufficiently erased memory cell is effected. The flash-erasing and erasing verification are repeatedly effected until no insufficiently erased memory cell is detected. When no insufficiently erased memory cell is detected, word lines other than a selected word line are set to a negative potential and an overerased memory cell is detected. When an overerased memory cell is detected, weak program is effected for the cell by applying a voltage lower than the normal writing voltage to the cell.

REFERENCES:
patent: 5233562 (1993-08-01), Ong et al.
patent: 5237535 (1993-08-01), Mielke et al.
patent: 5438544 (1995-08-01), Makino

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