Static information storage and retrieval – Read/write circuit – Testing
Patent
1992-04-21
1997-10-07
Swann, Tod R.
Static information storage and retrieval
Read/write circuit
Testing
36518901, 371 101, 371 211, 371 212, G11C 2900
Patent
active
056755449
ABSTRACT:
A memory circuit 14 is provided having a data register (20) coupled to the output of the memory cell array (16). The output of the data register (20) may be selectively output, allowing a plurality of memory circuits (14) to be tested in parallel with a substantial increase in efficiency. Furthermore, test data can be written to the memory cell arrays (14) while previous test data is read from the memory circuits for optimum efficiency.
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Donaldson Richard L.
Kempler William B.
Peikari J.
Swann Tod R.
Texas Instruments Incorporated
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