Non-volatile semiconductor memory device having a reference volt

Static information storage and retrieval – Floating gate – Particular biasing

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36518512, 36518513, G11C 1140

Patent

active

056755384

ABSTRACT:
Disclosed is a memory device which includes a memory cell array having a plurality of bit lines arranged in parallel, a plurality of word lines electrically insulated and crossed with the bit lines, and a plurality of memory cells connected with corresponding bit lines. Each of the memory cells has at least one floating gate memory transistor. A reference voltage generator generates a reference voltage that is applied to a sense line which corresponds to a selected word line that is selected when data is read out. Further, the present invention advantageously provides a discharging transistor that discharges the reference voltage on the sense line selected when the reading operation is complete in order to prevent application of a voltage to the floating gate of the memory cell for a period of time which is longer than necessary. As a result, undesired changes in the threshold voltage are minimized.

REFERENCES:
patent: 4677590 (1987-06-01), Arakawa
patent: 4785424 (1988-11-01), Lin et al.
patent: 4933906 (1990-06-01), Terada et al.

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