Separately addressable memory arrays in a multiple array semicon

Details Separately addressable memory arrays in a multiple array semicon Separately addressable memory arrays in a multiple array semicon

1985-01-22

1987-01-13

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Signals

365240, 365189, G11C 700

Patent

active

046369864

ABSTRACT:
A circuit for inhibiting data transfer to addressed memory locations in a plurality of arrays on a semiconductor chip includes an arbitration circuit (68) that distinguishes between separate inhibit signal inputs on dedicated CAS terminals and multiplexed inhibit signals on the input of an I/O buffer (66). The arbitration circuit (68) controls the enable circuits (64) for transferring data from the I/O buffer (66) to memory arrays (10), (12), (14) and (16). Separate inhibit signals allow multiple arrays to share common row and column decoders and maintain separate read/write capability.

REFERENCES:
patent: 4322635 (1982-03-01), Redwine
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4347587 (1982-08-01), Rao

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