Method for forming polish stop layer for CMP process

Details Method for forming polish stop layer for CMP process Method for forming polish stop layer for CMP process

1996-10-02

1997-10-07

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437228, 437235, 1566361, 1566621, H01L 21316

Patent

active

056747845

ABSTRACT:
A method is disclosed for planarizing interlevel dielectric layers in semiconductor wafers extremely smoothly. The key aspect of the disclosure is a buried stop layer that is ion implanted into the interlevel layer. It is shown that the stop layer can be formed at precise depths from the surface of the oxide layer and in a mostly planar surface. When the oxide layer with the buried stop layer is chemical/mechanically polished in the conventional manner, polishing stops at the stop layer yielding also a planar surface. The planarity of the polished surface can be extremely refined by first forming an extremely refined stop layer. The latter is accomplished by first planarizing the surface of the oxide layer in a number of ways before implanting the stop layer. It is further shown that when nitrogen atoms are used as the species for implanting, the resulting stop layer acquires a hardness very favorable for being differentiated from the softer oxide layer. Such abrupt difference in hardness provides a very precise polishing endpoint. At the same time, overpolishing of the interlevel layer is avoided.

REFERENCES:
patent: 4438556 (1984-03-01), Komatsu et al.
patent: 5246884 (1993-09-01), Jaso et al.
patent: 5593919 (1997-01-01), Lee et al.
S. Wolf, "Silicon Processing For The VLSI Era" vol. 2, Lattice Press, Sunset Beach, CA, pp. 196, 214-215, 234.

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