Fishing – trapping – and vermin destroying
Patent
1996-04-01
1997-10-07
Bowers, Jr., Charles L.
Fishing, trapping, and vermin destroying
437228, 437235, 437238, 1566361, H01L 21316
Patent
active
056747837
ABSTRACT:
A method for forming an insulator layer with enhanced uniformity when planarized through a Chemical-Mechanical Polish (CMP) planarizing process. There is first provided a semiconductor substrate having formed thereupon a patterned layer. The patterned layer has a volume density greater than the volume density of an insulator layer to be formed upon the patterned layer. The patterned layer also has a first region having a high areal density of the patterned layer and a second region having a low areal density of the patterned layer. The second region of the patterned layer is then masked. The first region of the patterned layer is then exposed to a first plasma which is capable of modifying the first region of the patterned layer such that the insulator layer will form less rapidly upon the first region of the patterned layer than upon the second region of the patterned layer. The second region of the semiconductor substrate is then unmasked and the insulator layer is formed upon the patterned layer. The insulator layer so formed being thicker over the second region than over the first region. As a first alternative the first region of the patterned layer may be masked and the second region of the patterned layer exposed to a second plasma which enhances the growth of the insulator layer. As a second alternative, both the first plasma and the second plasma may be employed through sequential masking steps.
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Jang Syun-Ming
Yu Chen-Hua Douglas
Ackerman Stephen B.
Bowers Jr. Charles L.
Saile George O.
Szecsy Alek P.
Taiwan Semiconductor Manufacturing Company , Ltd.
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