Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1995-05-10
2000-04-18
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
G06F 1130, G06F 1200
Patent
active
06052801&
ABSTRACT:
A method and apparatus for providing breakpoints on a selectable address range. The apparatus generally includes a processor including a first storage area, a second storage area, a circuit and an execution unit. The first storage area has stored therein a first address, while the second storage area has stored therein a mask. The first address and the mask define an address range. In response to receiving a second address, the circuit accesses the first address stored in the first storage area and the mask stored in the second storage area. The circuit transmits a signal to cause a debug event if the second address is within the address range defined by the first address and the mask.
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Alpert Donald
Hammond Gary N.
Intel Corporation
Nguyen Hoa T.
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