Method and apparatus for reducing system snoop latency

Details Method and apparatus for reducing system snoop latency Method and apparatus for reducing system snoop latency

1996-12-02

2000-04-18

Auve, Glenn A.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395308, G06F 1208

Patent

active

060527625

ABSTRACT:
In multi-processor systems which have separated the system bus from the I/O bus, a Shadow Directory is introduced into the memory controller for reducing bottlenecks that occur from the processors snooping data cache in the I/O devices residing on the I/O bus. This Shadow Directory is advantageously employed in a system, such as the PowerPc architecture which distinguishes between the types of data that can be cached in I/O devices. The Shadow Directory uses two First In First Out (FIFO) stacks for two different types of data. These FIFO stacks are then used for addresses placed on the system bus and I/O bus in order to reduce snoop latency times.

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