Structure and fabrication method for EEPROM memory cell with sel

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257321, 257322, 257402, 257404, 437 40, 437 45, H01L 2968, H01L 21265

Patent

active

052312992

ABSTRACT:
An electrically programmable and electrically erasable memory cell (EEPROM) formed in a silicon body is described. The cell includes a silicon body or substrate with shallow trench isolation regions disposed therein. First and second spaced-apart source and drain regions of a first conductivity type are provided with a channel region in between. A first gate member, a floating gate, which is completely surrounded by insulation extends from at least the edge of the source region, over the channel region to at least the edge of the drain region. A second gate member, a control gate, includes a portion which extends over the floating gate. The control gate extends from at least the edge of the source region, over the channel region to at least the edge of the drain region. The channel region beneath the floating gate has both a highly doped portion and a lightly doped portion. The fabrication process of the EEPROM cell is also disclosed and includes the steps of low and high dose channel implantation, formation of the floating gate and control gate, and formation of the source and drain elements.

REFERENCES:
patent: 4974051 (1990-11-01), Matloubian et al.

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