Semiconductor memory apparatus

Details Semiconductor memory apparatus Semiconductor memory apparatus

1994-10-25

1996-08-20

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257390, 257305, 257630, H01L 27108

Patent

active

055481450

ABSTRACT:
A semiconductor memory device comprises a semiconductor substrate having memory cell area, a plurality of trenches selectively formed in the memory cell area aligning in certain intervals and a plurality of memory cell arrays provided in the memory cell area, wherein each of the memory cell arrays comprises a plurality of MOS transistors connected in a serial array and a plurality of capacitors each formed in a corresponding one of the trenches. Each of the transistors has a gate electrode above the substrate with a gate insulating film formed therebetween and source and drain regions formed in the substrate on both sides of the gate electrode. Each of the capacitors includes a charge storage layer formed on an inner wall of each of the trenches and connected integrally to one of the source and drain regions of each of the transistors, a capacitor insulating film formed on the charge storage layer and a capacitor electrode formed on the capacitor insulating film so as to bury each of the trenches and extending to the surface of the substrate, which is formed on the surface of the substrate except for at least formation areas of the transistors.

REFERENCES:
patent: 4785337 (1988-11-01), Kenney
patent: 5057887 (1991-10-01), Yashiro et al.
patent: 5245205 (1993-09-01), Higasitani et al.
Takeshi Hamamoto, et al., "NAND-Structured Cell Technologies For Low Cost 256Mb DRAMs", 1993 IEEE IEDM Technical Digest, 1993, pp. 643-646.
Don Stark, et al., "An Experimental Cascade Cell Dynamic Memory", 1994 Symposium on VLSI Circuits Digest of Technical Papers, 1994, pp. 89-90.
Katsutaka Kimura, et al., "A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-Line Architecture", 1991 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 1991, pp. 106-107.
Takehiro Hasegawa, et al., "WP 3.3: An Experimental DRAM with a NAND-Structured Cell", 1993 IEEE International Solid-state Circuits Conference Digest of Technical Papers, 1993, pp. 46-47.
Shinichiro Shiratake, et al., "A Staggered NAND DRAM Array Architecture for a Gbit Scale Integration", 1994 Symposium on VLSI Circuits Digest of Technical Papers, 1994, pp. 75-76.

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