Data output buffer using pass transistors biased with a referenc

Electronic digital logic circuitry – Interface – Current driving

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Details

326 17, 326 58, 326113, H03K 190185

Patent

active

056336039

ABSTRACT:
A data output buffer circuit for a semiconductor device for transferring read cell data to the peripheral circuits, comprising an input terminal for inputting the read cell data, a first NMOS transistor for transferring the data from the input terminal when it has a first logic level, a first PMOS transistor for transferring the data from the input terminal when it has a second logic level, a second PMOS transistor for transferring a high logic signal in response to an output signal from the first NMOS transistor, a second NMOS transistor for transferring a low logic signal in response to an output signal from the first PMOS transistor, and an output terminal for outputting the high logic signal from the second PMOS transistor or the low logic signal from the second NMOS transistor to the peripheral circuits.

REFERENCES:
patent: 3739193 (1973-06-01), Pryor
patent: 4491749 (1985-01-01), Iwamura
patent: 4746818 (1988-05-01), Hafner
patent: 5111076 (1992-05-01), Tarng
patent: 5297097 (1994-03-01), Etoh et al.
patent: 5367645 (1994-11-01), Lubeck et al.
patent: 5512854 (1996-04-01), Park

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