Method for making self-aligned source/drain mask ROM memory cell

Details Method for making self-aligned source/drain mask ROM memory cell Method for making self-aligned source/drain mask ROM memory cell

1995-03-17

1997-01-21

Picardat, Kevin

Fishing, trapping, and vermin destroying

437 40, 437 41, 437203, H01L 2170

Patent

active

055959270

ABSTRACT:
A device and a method are provided for manufacture of that semiconductor memory device on a silicon semiconductor substrate with a vertical channel. A dielectric layer pattern with openings through it is formed. Trenches are formed in the surface of the semiconductor substrate. The trenches have sidewalls. A spacer layer is formed on the surface of the device. The spacer layer is shaped to form spacers in the trenches on the sidewalls. Source/drain regions are formed by ion implanting ions to deposit dopant into the substrate. The device is annealed to form source/drain regions in the substrate. A dielectric layer is formed over the device. A conductive word-line is formed and patterned over the dielectric layer.

REFERENCES:
patent: 5180680 (1993-01-01), Yang
patent: 5183774 (1993-02-01), Satoh
patent: 5196368 (1993-03-01), Thompson et al.
patent: 5244824 (1993-09-01), Sivan
patent: 5429973 (1995-07-01), Hong
patent: 5460988 (1995-10-01), Hong
patent: 5488009 (1996-01-01), Hsue et al.

Affiliated with

Also associated with

Rating

Method for making self-aligned source/drain mask ROM memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for making self-aligned source/drain mask ROM memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making self-aligned source/drain mask ROM memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2323889