System for generating chip select signals based on coded and unc

Details System for generating chip select signals based on coded and unc System for generating chip select signals based on coded and unc

1998-01-02

2000-01-25

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Storage accessing and control

36518908, 365194, 326 39, 711154, G06F 1200, G06F 1300

Patent

active

060187875

ABSTRACT:
A chip selection enable apparatus which outputs one of plural chip enable signals in correspondence to which of plural address signals appear on an address bus. The chip selection apparatus includes a programmable array logic device, connectable to the address bus, which is programmed to output at least one chip enable signal in response to address signals on the address bus, and which is also programmed to output N (N>1) coded signals in response to other address signals on the address bus. A decoder is connected to the programmable array logic device and decodes the N coded signals into at least N+1 chip enable signals. In one preferred embodiment, the programmable array logic device is configured to output five chip enable signals and three coded signals. A standard one-of-eight binary decoder decodes the three coded signals into eight additional chip enable signals, thereby providing 13 chip enable signals from a single programmable array logic device, even though the programmable array logic device is capable of outputting only eight outputs.

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K.J. Whiteley, "EPROM decoder for device selection", Electronic Engineering, vol. 58, No. 714, Jun. 1986, p. 36.
"Method For Address Decode For Input/Output Devices" IBM Technical Disclosure Bulletin, vol. 31, No. 8, Jan. 1989, pp. 202-203.

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