Interface circuit for controlling data transfers

Details Interface circuit for controlling data transfers Interface circuit for controlling data transfers

1993-10-04

1995-10-10

Harrell, Robert B.

Boots, shoes, and leggings

364DIG1, 364DIG2, 3642362, 3642412, 3642481, 364260, 364941, 3649411, G06F 1314

Patent

active

054577870

ABSTRACT:
An interface circuit for a peripheral device is disclosed that can accurately cope with any host with the same hardware whether the host is in the pre-read mode or the post-read mode and can send an interrupt request to the host practically without a waiting time if the host is in the post-read mode. The interface circuit generates an interrupt request (IRQ) to a host in response to a data request (DRQ) from a peripheral device (HDD) and drops the interrupt request if the status of the peripheral device is read by the host; it detects that the host operates in a post-read mode, and responds to the post-read mode detect signal and the status reading by the host in order to enable the regeneration of the interrupt request to the host.

REFERENCES:
patent: 4509113 (1985-04-01), Heath
patent: 4607328 (1986-08-01), Furukawa et al.
patent: 4947366 (1990-08-01), Johnson
patent: 5014237 (1991-05-01), Masters et al.

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