Method and circuit configuration for debiting a debit card

Details Method and circuit configuration for debiting a debit card Method and circuit configuration for debiting a debit card

1994-05-10

1996-04-23

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

36518509, 365201, 365218, 365236, 235492, G11C 700

Patent

active

055110231

ABSTRACT:
A debit card carries an integrable electronic circuit which is electronically debited. The circuit includes a nonvolatile, electrically erasable and writable memory operated as a multi-stage counter with counter stages. The circuit is provided with a nonvolatile, electrically erasable and writable check memory which has check memory regions associated with respective counter stages of the counter memory. The card is debited in that at least one of the memory cells of a memory is read out with at least two different weighting thresholds, and the counter memory is controlled as a function of the results obtained in that reading. The reading of the carry bit and the associated check bit allow to safely prevent against manipulation and the circuit may be realized at a very low expense.

REFERENCES:
patent: 5001332 (1991-03-01), Schrenk
patent: 5285415 (1994-02-01), Depret et al.
patent: 5383147 (1995-01-01), Saneritsu
patent: 5410714 (1995-04-01), Yorimoto et al.
patent: 5420412 (1995-05-01), Kowalski

Affiliated with

Also associated with

Rating

Method and circuit configuration for debiting a debit card does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and circuit configuration for debiting a debit card, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and circuit configuration for debiting a debit card will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2314594