Dynamic random access memory with improved page-mode performance

Details Dynamic random access memory with improved page-mode performance Dynamic random access memory with improved page-mode performance

1991-02-25

1993-08-31

Sikes, William L.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365208, 365190, 36518905, 3652385, G11C 700, G11C 800

Patent

active

052415031

ABSTRACT:
A dynamic random access memory includes memory cells located at intersections of word lines and differential bit line pairs. A row decoder activates a word line in response to a row address. A first sense amplifier coupled to each bit line pair then increases the small differential voltage of the bit line pair to positive and negative power supply voltages. The first sense amplifier is then isolated from the bit lines so that the bit lines may be equalized. The contents of memory cells along the activated word line are stored in corresponding first sense amplifiers, and the memory functions as a by-one static random access memory during successive page-mode cycles. At the end of the page-mode cycles, the first sense amplifiers are recoupled to the bit lines, and second sense amplifiers update modified data and refresh the charge stored in the memory cells. Performance is improved in at least three ways, including improved write speed, decreased SER by reducing subthreshold leakage, and reduced power consumption.

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patent: 5127739 (1992-07-01), Duooury et al.

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