Semiconductor memory device for detecting defective memory cells

Details Semiconductor memory device for detecting defective memory cells Semiconductor memory device for detecting defective memory cells

1990-10-19

1993-08-31

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

365200, 371 211, G11C 1134

Patent

active

052415015

ABSTRACT:
A DRAM with a word line shifting circuit (6) is disclosed. In an externally specified test mode, a word line shifting circuit sequentially selects two word lines (WL.sub.i, WL.sub.i+1) A test data stored in a memory cell (101) is shifted through bit lines (BL, BL) to an adjacent other memory cell (102). This shifting operation is repeated between two adjacent memory cells. By comparing the repetitive shifted test data with the primarily supplied test data, the detection of whether or not a defective memory cell exists in the memory cell connected to the bit lines is accomplished in a short time.

REFERENCES:
patent: 3760368 (1973-09-01), Dailey et al.
patent: 4326290 (1982-04-01), Davis et al.
patent: 4464750 (1984-08-01), Tatematsu
patent: 4920515 (1990-04-01), Obata
Kazutami Arimoto et al., "A 60ns 3.3V 16Mb DRAM", IEEE International Solid-State Circuits Conference, Session 16: Dynamic RAMs, pp. 244-245, Feb. 17, 1989.
IEEE Publication entitled "A 90ns 1Mb DRAM with Multi-bit Test Mode", IEEE International Solid-State Conference, 1985, by Kumanoya et al.

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