Programmable multibit register for coincidence and jump operatio

Details Programmable multibit register for coincidence and jump operatio Programmable multibit register for coincidence and jump operatio

1996-01-26

1998-03-24

Hudspeth, David R.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326 13, 326 37, 365200, H03K 19177

Patent

active

057317160

ABSTRACT:
A programmable cell and a multibit register composed of a plurality of such cells, specifically for performing a coincidence check between a certain code permanently recorded in the cell or cells and a logic configuration present on a pair or on a plurality of pairs of control lines are disclosed. Each cell has two branches connected in OR configuration to a common sensing line of the cell or of the multibit register. The logic states to be tested for coincidence are applied in a complemented form through a pair of lines to each cell, that is to the two branches of the cell. Each cell, permanently programmed in one or the other of its branches, intrinsically performs a comparison between its permanently programmed logic configuration and the configuration of the complemented control lines associated therewith. A great simplification is achieved in the overall circuitry of a redundance or reconfiguration system.

REFERENCES:
patent: 4672240 (1987-06-01), Smith et al.
patent: 4791319 (1988-12-01), Tagami et al.
patent: 5559743 (1996-09-01), Pascucci et al.
patent: 5561621 (1996-10-01), Devin et al.
IBM Technical Disclosure Bulletin, vol. 17, No. 10, Mar. 1975, New York, pp. 2897-2899 S. Dasgupta, "Array logic structure using FAMOS devices".
Patent Abstracts of Japan, vol. 18, No. 216 (P-1728), Apr. 1994, & JP-A-06 021884 (NEC Corp.), Jan. 1994.

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