Semiconductor device with reduced parasitic substrate capacitanc

Details Semiconductor device with reduced parasitic substrate capacitanc Semiconductor device with reduced parasitic substrate capacitanc

1996-09-05

1998-03-24

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257776, 257786, H01L 2348

Patent

active

057316201

ABSTRACT:
An N-type semiconductor layer 12 is formed on a P-type semiconductor base 11, and an insulating film 13 and a pad 16 are formed on the semiconductor layer 12. A P-type isolating diffusion layer 20 is formed in part of the semiconductor layer 12 below the insulating film 13. An N-type impurity diffusion layer 17 connected to the semiconductor layer 12 is formed on the semiconductor layer 12, and an electrode 19 connected to the impurity diffusion layer 17 through a connecting hole 18 formed in the insulating film 13 above the impurity diffusion layer 17 is so formed that it is electrically independent from the pad 16. The isolating diffusion layer 20 is formed outside the outer periphery of the impurity diffusion layer 17 and so that the PN junction between the semiconductor base 11 and the semiconductor layer 12 exists in at least a part of the area below the pad 16. In this semiconductor device, because the PN junction between the semiconductor base and the semiconductor layer exists in at least a part of the area below the pad, this PN junction capacitance is connected in series with the pad. As a result, the parasitically connected so-called substrate (semiconductor base) capacitance is reduced. Also, by impressing a reverse field across the semiconductor layer and the semiconductor base from this electrode 19, the PN junction capacitance can be reduced in the width of a depletion layer.

REFERENCES:
patent: 5243219 (1993-09-01), Katayama

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